METHOD OF FORMING VERTICAL CHANNEL DEVICES

• US 20180342584A1
• Filed: 05/15/2018
• Published: 11/29/2018
• Est. Priority Date: 05/15/2017
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Boemmels, Juergen
• Granted Patent: US 10,546,930 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

The disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices. In one aspect, a method of forming vertical channel devices includes providing a semiconductor structure that includes a substrate and a plurality of vertical channel structures. The method additionally includes surrounding the vertical channel structures with respective wrap-around gates. The method additionally includes forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures. The method further includes forming a top electrode on each of the enlarged top portions.

Claims

1. A method of forming vertical channel devices, the method comprising:

providing a substrate and forming thereon a plurality of vertical channel structures;

surrounding each of the vertical channel structures with respective wrap-around gates;

forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures; and

forming a top electrode on each of the enlarged top portions.

2. The method according to claim 1, further comprising, prior to growing the doped semiconductor material, forming a dielectric layer embedding the wrap-around gates, wherein the dielectric layer exposes the top portions of the at least the subset of the vertical channel structures.

3. The method according to claim 1, wherein forming the enlarged top portions comprises growing a first doped semiconductor material selectively on top portions of a first selected subset of the vertical channel structures, and growing a second doped semiconductor material selectively on top portions of a second selected subset of the vertical channel structures.

4. The method according to claim 3, wherein the first semiconductor material is doped with a first dopant type and the second semiconductor material is doped with a second dopant type opposite the first dopant type.

5. The method according to claim 3, further comprising:

forming a first mask covering the top portions of the vertical channel structures of the second selected subset and exposing the top portions of the vertical channel structures of the first selected subset,

wherein the first doped semiconductor material is grown selectively on each of the top portions exposed by the first mask;

removing the first mask; and

forming a second mask covering the top portions of the vertical channel structures of the first selected subset and exposing the top portions of the vertical channel structures of the second selected subset,

wherein the second doped semiconductor material is grown selectively on each of the top portions exposed by the second mask.

6. The method according to claim 5, further comprising:

forming a first mask layer covering the top portions of the plurality of vertical channel structures;

forming a first mask patterning layer on the first mask layer;

opening the first mask patterning layer in a region above the top portions of the vertical channel structures of the first selected subset;

opening the first mask layer in a region exposed in the opening of the first mask patterning layer, wherein the opened first mask layer forms the first mask; and

prior to growing the first semiconductor material, implanting ions into the top portions exposed by the first mask, wherein the ion are blocked from being implanted into regions covered by the first mask.

7. The method according to claim 6, further comprising removing the first mask patterning layer subsequent to implanting the ions and prior to growing the first semiconductor material.

8. The method according to claim 1, wherein forming the top electrode comprises:

forming a top electrode layer including forming at least a first conductive layer, the top electrode layer being formed on a dielectric layer embedding the gates, the top electrode layer covering the enlarged top portions of the vertical channel structures; and

using a top electrode pattern as an etch mask to pattern the top electrode layer into the top electrodes.

9. The method according to claim 8, wherein forming the top electrode layer further includes forming a second conductive layer formed on the first conductive layer, wherein at least the first conductive layer is formed as a conformal layer on the dielectric layer and the enlarged top portions of the vertical channel structures.

10. The method according to claim 8, wherein patterning the top electrode layer includes:

forming a top electrode mask layer on the top electrode layer;

forming the top electrode pattern in the top electrode mask layer, the top electrode pattern including a set of discrete mask portions, each of the mask portions overlapping at least one enlarged top portion along a vertical direction; and

etching the top electrode layer in regions exposed by the set of discrete mask portions of the top electrode pattern such that a set of discrete top electrodes are formed.

11. The method according to claim 1, further comprising:

subsequent to forming the top electrode, forming a sidewall etch barrier on sidewalls of the top electrode;

forming an additional dielectric layer covering the dielectric layer and the top electrode; and

etching a set of vertically extending gate contact holes through the additional dielectric layer and the dielectric layer and adjacent to a top electrode, each hole exposing one of the gates, wherein etching the holes is performed selectively against the sidewall etch barrier, and subsequently filling the set of gate contact holes with a conductive material.

12. The method according to claim 11, wherein forming the set of vertically extending gate contact holes includes:

forming a gate contact mask layer above the additional dielectric layer;

forming openings in the gate contact mask layer, the openings defining the locations of the holes; and

etching the dielectric and additional dielectric layers by using the gate contact mask layer as an etch mask.

13. The method according to claim 11, further comprising forming an upper etch barrier on the top electrodes, wherein etching the dielectric and additional dielectric layers includes etching the dielectric and additional dielectric layers selectively against the sidewall etch barrier and against the upper etch barrier.

14. The method according to claim 11, further comprising:

subsequent to forming the additional dielectric layer, forming a set of vertically extending top contact holes, each hole exposing a top electrode and each hole being formed by etching the additional dielectric layer; and

filling the set of top contact holes with the conductive material.

15. The method according to claim 14, wherein the set of gate contact holes and the set of top contact holes are filled with the conductive material by forming a conductive material layer covering the additional dielectric layer and filling the set of gate contact holes and the set of top contact holes.