SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK

• US 20180342600A1
• Filed: 08/06/2018
• Published: 11/29/2018
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Yi-Jen, Chen, Chang-Yin, Chang, Yung Jung
• Granted Patent: US 10,879,372 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Claims

1. A semiconductor device, comprising:

a metal gate stack comprising a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric, wherein;

the high-k gate dielectric has a tapered sidewall, and

the metal gate electrode has a tapered sidewall.

2. The semiconductor device of claim 1, wherein the metal gate stack comprises a cap layer between the high-k gate dielectric and the metal gate electrode.

3. The semiconductor device of claim 2, wherein the cap layer has a tapered sidewall.

4. The semiconductor device of claim 3, wherein the tapered sidewall of the high-k gate dielectric, the tapered sidewall of the metal gate electrode, and the tapered sidewall of the cap layer have a common slope.

5. The semiconductor device of claim 1, wherein the tapered sidewall of the high-k gate dielectric and the tapered sidewall of the metal gate electrode have a common slope.

6. The semiconductor device of claim 1, wherein the metal gate stack comprises an interfacial layer below the high-k gate dielectric.

7. The semiconductor device of claim 6, wherein the interfacial layer has a tapered sidewall.

8. The semiconductor device of claim 7, wherein the tapered sidewall of the high-k gate dielectric, the tapered sidewall of the metal gate electrode, and the tapered sidewall of the interfacial layer have a common slope.

9. The semiconductor device of claim 6, wherein the metal gate stack comprises a cap layer between the high-k gate dielectric and the metal gate electrode.

10. The semiconductor device of claim 9, wherein:

the interfacial layer has a tapered sidewall, and

the cap layer has a tapered sidewall.

11. The semiconductor device of claim 10, wherein the tapered sidewall of the high-k gate dielectric, the tapered sidewall of the metal gate electrode, the tapered sidewall of the interfacial layer, and the tapered sidewall of the cap layer have a common slope.

12. A semiconductor device, comprising:

a metal gate stack comprising a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric, wherein;

the metal gate electrode comprises a top surface and a bottom surface,

a length of the top surface is greater than a length of the bottom surface.

13. The semiconductor device of claim 12, wherein the metal gate stack comprises an interfacial layer below the high-k gate dielectric and in contact with a substrate, wherein a sidewall of the interfacial layer abut a top surface of the substrate at a non-perpendicular angle.

14. The semiconductor device of claim 12, wherein the metal gate stack comprises a cap layer between the high-k gate dielectric and the metal gate electrode.

15. The semiconductor device of claim 14, wherein the cap layer is at least one of gold, tin, silver, or titanium nitride.

16. The semiconductor device of claim 14, wherein the cap layer is in contact with the high-k gate dielectric and the metal gate electrode.

17. The semiconductor device of claim 12, comprising a sidewall spacer adjacent the metal gate stack and in contact with a substrate underlying the metal gate stack.

18. The semiconductor device of claim 17, wherein an interior angle of the sidewall spacer, defined by a top surface of the substrate and a sidewall of the sidewall spacer that faces the metal gate stack, is less than 90 degrees.

19. A semiconductor device, comprising:

a metal gate stack comprising an interfacial layer, a high-k gate dielectric over the interfacial layer, and a metal gate electrode over the high-k gate dielectric, wherein;

a length of a bottom surface of the high-k gate dielectric is greater than or equal to a length of a top surface of the interfacial layer,

a length of a top surface of the high-k gate dielectric is greater than the length of the bottom surface of the high-k gate dielectric, and

a length of a bottom surface of the metal gate electrode is greater than or equal to the length of the top surface of the high-k gate dielectric.

20. The semiconductor device of claim 19, wherein:

a length of the top surface of the interfacial layer is greater than a length of a bottom surface of the interfacial layer, and

a length of a top surface of the metal gate electrode is greater than the length of the bottom surface of the metal gate electrode.