Dynamic Read Table Block Filter

• US 20180350446A1
• Filed: 08/15/2017
• Published: 12/06/2018
• Est. Priority Date: 06/03/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: K, Narayan, Desireddi, Sateesh, Puthoor, Aneesh, Krishna, Dharmaraju Marenahally, Thandapani, Arun, Prasad, Divya, Murugaiyan, Thendral, Dhotre, Piyush
• Granted Patent: US 10,553,301 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.

Claims

1. An apparatus, comprising:

a plurality of memory cells;

a maintenance circuit configured to identify a set of memory cells storing data to be reprogrammed, the set of memory cells having a projected error bit rate;

a test circuit configured to test the set of memory cells to determine an error bit rate, the test circuit comprising a compensation circuit configured to compensate for a temperature difference between when the cells are programmed and when the test circuit performs the test; and

a management circuit configured to mark the set of memory cells to receive a maintenance operation in response to the error bit rate satisfying a threshold.

2. The apparatus of claim 1, wherein:

the management circuit is configured to mark the set of memory cells to not receive the maintenance operation, in response to the error bit rate not satisfying the threshold.

3. The apparatus of claim 2, further comprising,

a pre-test circuit configured to test the set of memory cells to determine an initial error bit rate without compensating for the temperature difference;

and

the management circuit is configured to exclude the set of memory cells from the maintenance operation in response to the initial error bit rate satisfying a threshold.

4. The apparatus of claim 3, wherein:

the pre-test circuit is configured to determine the initial error bit rate by sensing the set of memory cells for a data state using a first reference level;

the test circuit is configured to determine the error bit rate by sensing the set of memory cells for the data state using a second reference level, the second reference level higher than the first reference level.

5. The apparatus of claim 4, wherein:

the data state is a second data state;

the pre-test circuit is configured to determine the initial error bit rate by sensing the set of memory cells for a first data state using a third reference level, the first data state is associated with lower threshold voltages than the second data state; and

the test circuit is configured to determine the error bit rate by sensing the set of memory cells for the first data state using the third reference level.

6. The apparatus of claim 3, wherein:

the test circuit is configured to determine the initial error bit rate in response to determining that a reprogram queue includes the set of memory cells;

the management circuit is configured to remove the set of memory cells from the reprogram queue in response to the initial error bit rate not satisfying the threshold; and

the management circuit is configured to remove the set of memory cells in response to the error bit rate not satisfying the threshold.

7. The apparatus of claim 1, wherein the error bit rate is a selected error bit rate, the test circuit is configured to determine the selected error bit rate by:

performing a first read operation using a first set of read levels for a first set of states and determining a first error bit rate;

performing a second read operation using a second set of read levels for the first set of states and determining a second error bit rate, the first and second set of read levels including different read levels for a first state; and

selecting the lower of the first error bit rate and the second error bit rate as the selected error bit rate.

8. The apparatus of claim 1, wherein:

the test circuit is configured to compensate for the temperature difference as part of determining the error bit rate during a read scan; and

the management circuit is configured to mark the set of memory cells to receive the maintenance operation by adding the set of memory cells to a reprogram queue.

9. The apparatus of claim 1, wherein the set of memory cells is a first set of memory cells, the apparatus further comprising:

a reprogram circuit configured to read data associated with the first set and program the data to a second set of memory cells

10. The apparatus of claim 1, wherein:

the set of memory cells is part of a group of memory cells coupled to a plurality of word lines and a plurality of bit lines; and

the management circuit is configured to mark the group of memory cells to receive the maintenance operation in response to the error bit rate satisfying the threshold.

11. The apparatus of claim 1, further comprising:

a plurality of NAND strings including the plurality of memory cells, the plurality of NAND strings are arranged in a three-dimensional structure;

a plurality of bit lines coupled to the plurality of NAND strings;

a plurality of word lines coupled to the plurality of NAND strings; and

a source line coupled to the plurality of NAND strings.

12. The apparatus of claim 1, wherein:

the test circuit configured to determine a current temperature associated with the set of memory cells and a programmed temperature associated with the set of memory cells;

the test circuit configured to determine the error bit rate by sensing the set of memory cells for a first data state using a first reference level, in response to the current temperature less than the programmed temperature; and

the test circuit configured to determine the error bit rate by sensing the set of memory cells for the first data state using a second reference level, in response to the current temperature greater than the programmed temperature.

13. The apparatus of claim 1, further comprising:

a read table configured to store one or more temperature compensations for sensing a plurality of data states associated with the set of memory cells, wherein the one or more temperature compensations include compensations for less than all of the plurality of data states;

wherein the test circuit is configured to access the read table and determine the error bit rate by sensing the set of memory cells based on the temperature compensation.

14. An apparatus, comprising:

a plurality of memory cells;

a sense circuit configured to sense a set of memory cells of the plurality and determine an error associated with sensing the set;

a compensation circuit configured to compensate for temperature changes as part of sensing to determine the error; and

a reprogram circuit configured to reprogram data of the set of memory cells based on the error satisfying a threshold.

15. The apparatus of claim 14, further comprising:

a reprogram queue configured to identify memory cells for reprogramming; and

a management circuit configured to retain the set of memory cells in the reprogram queue in response to the error satisfying the threshold;

wherein the reprogram circuit is configured to reprogram the data of the set of memory cells in response to the reprogram queue including the set of memory cells after the compensation circuit applies the temperature compensation.

16. The apparatus of claim 14, wherein:

the compensation circuit is configured to compensate for temperature changes by using one or more compensated read levels during reading associated with the set.

17. The apparatus of claim 16, wherein:

the sense circuit is configured to apply a first default read voltage during sensing for a first state to determine the error; and

the first state is associated with lower threshold voltages than a second state.

18. A method, comprising:

sensing at least one set of memory cells from a group of cells in response to a reprogramming designation associated with the group, wherein the sensing includes at least one temperature compensation;

determining that an error associated with sensing the at least one set of memory cells is below a threshold; and

removing the reprogramming designation associated with the group in response to the error being below the threshold.

19. The method of claim 18, wherein:

sensing with at least one temperature compensation comprises applying at least one compensated read voltage.

20. The method of claim 19, wherein the group is a first group and the error is a first error, the method further comprises:

determining that a second group of memory cells is associated with a reprogramming designation;

sensing at least one set of memory cells of the second group, wherein sensing the at least one set of the second group comprises using a default read voltage;

determining that a second error associated with sensing the at least one set of the second group is below the threshold; and

removing a reprogramming designation associated with the second group in response to the second error being below the threshold.

21. The method of claim 19, wherein the error is a second error, the method further comprises:

sensing the at least one set from the group using a default read voltage prior to sensing with at least one temperature compensation; and

determining that a first error is above the threshold;

wherein sensing with at least one temperature compensation is performed in response to determining that the first error is above the threshold.

22. An apparatus, comprising:

a plurality of memory cells;

means for determining an error associated with sensing a set of memory cells from the plurality;

means for applying a temperature compensation as part of sensing to determine the error, wherein the temperature compensation compensates for cells that are programmed at a first ambient temperature and read at a different second ambient temperature; and

means for reprogramming data from the set of memory cells into the plurality of memory cells in response to the error satisfying a threshold.