Flat Metal Features for Microelectronics Applications
First Claim
1. A method, comprising:
- providing a substrate with at least one cavity at a surface;
forming a conductive layer inside and outside the cavity, wherein a conductive layer within the cavity is thicker than a conductive layer outside the cavity;
annealing the substrate to generate larger metal grains in the cavity and smaller metal grains outside the cavity;
polishing the conductive layers, wherein the larger metal grains resist the polishing more than the smaller metal grains; and
wherein the polishing removes the conductive layer outside the cavity while forming a flat conductive feature in the cavity with a dishing defect of less than 3 nanometers per 10 micron width of the flat conductive feature.
3 Assignments
0 Petitions
Accused Products
Abstract
Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
5 Citations
25 Claims
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1. A method, comprising:
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providing a substrate with at least one cavity at a surface; forming a conductive layer inside and outside the cavity, wherein a conductive layer within the cavity is thicker than a conductive layer outside the cavity; annealing the substrate to generate larger metal grains in the cavity and smaller metal grains outside the cavity; polishing the conductive layers, wherein the larger metal grains resist the polishing more than the smaller metal grains; and wherein the polishing removes the conductive layer outside the cavity while forming a flat conductive feature in the cavity with a dishing defect of less than 3 nanometers per 10 micron width of the flat conductive feature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10)
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8. (canceled)
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11-13. -13. (canceled)
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14. A method, comprising:
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creating trenches or cavities for metal features in a substrate suitable for a microelectronic device; covering the substrate with a metal to create both a cavity layer of the metal at least partially filling the cavities and a field layer of the metal covering a field of the substrate with the metal; thermally annealing the metal to create grains of the metal in the cavity layer of the metal that are larger than grains of the metal in the field layer of the metal; and planarizing at least the grains of the metal in the cavity layer of the metal to achieve flat conductive metal features of the microelectronic device. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25-64. -64. (canceled)
Specification