GATE FORMATION WITH VARYING WORK FUNCTION LAYERS

• US 20180350955A1
• Filed: 05/31/2017
• Published: 12/06/2018
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Jin-Dah, Chen, Stan, Wu, Han-Wei
• Granted Patent: US 10,644,134 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.

Claims

1. A method comprising:

forming a first dielectric layer over a first fin and a second fin;

forming a recess in the first dielectric layer, the first fin and the second fin protruding above a bottom of the recess;

forming a first work function layer over the first fin and the second fin;

forming a first patterned mask over the first work function layer, the first patterned mask terminating closer to the first fin than the second fin such that the first work function layer over the second fin is exposed;

removing the first work function layer from over the second fin and an area between the first fin and the second fin, the first work function layer terminating at a position closer to the first fin than the second fin;

removing the first patterned mask;

forming a second work function layer over the first work function layer and the second fin;

forming a second patterned mask over the second work function layer, the second patterned mask terminating closer to the second fin than the first fin such that the second work function layer over the second fin is exposed;

removing the second work function layer from over the second fin and an area between the first fin and the second fin, the second work function layer terminating at a position closer to the second fin than the first fin;

removing the second patterned mask;

forming a third work function layer over the second work function layer and the second fin; and

forming a metal layer over the third work function layer.

2. The method of claim 1, further comprising forming a gate dielectric over the first fin and the second fin prior to forming the first work function layer.

3. The method of claim 1, wherein the first work function layer extends along sidewalls of the recess.

4. The method of claim 3, wherein the second work function layer extends along sidewalls of the recess.

5. The method of claim 1, wherein forming the first patterned mask comprises:

forming a first masking layer over the first work function layer, the first masking layer filling the recess;

forming a first photoresist layer over the first masking layer;

patterning the first photoresist layer to form a first patterned photoresist layer; and

patterning the first masking layer using the first patterned photoresist layer as a mask.

6. The method of claim 5, wherein forming the second patterned mask comprises:

forming a second masking layer over the second work function layer, the second masking layer filling the recess;

forming a second photoresist layer over the second masking layer;

patterning the second photoresist layer to form a second patterned photoresist layer; and

patterning the second masking layer using the second patterned photoresist layer as a mask.

7. The method of claim 1, wherein a distance from first fin to an edge of the first work function layer is 10 nm to 40 nm.

8. The method of claim 7, wherein a distance from the first fin to an edge of the second work function layer is 20 nm to 90 nm.

9. A method comprising:

forming a first work function layer over a first fin, the first work function layer terminating closer to the first fin than a second fin;

forming a second work function layer over the first work function layer, the second work function layer terminating closer to the second fin than the first fin;

forming a third work function layer over the second work function layer, the third work function layer extending over the second fin; and

forming a metal layer over the third work function layer.

10. The method of claim 9, wherein the metal layer is a gate electrode.

11. The method of claim 9, further comprising, prior to forming the first work function layer:

forming a dielectric layer over the first fin and the second fin; and

forming a recess in the dielectric layer, the first fin and the second fin protruding through a bottom of the recess.

12. The method of claim 11, wherein the first work function layer and the second work function layer are formed along sidewalls of the recess.

13. The method of claim 12, wherein a width of the recess is from 100 nm to 2000 nm.

14. The method of claim 9, wherein a thickness of the first work function layer is 5 Å

to 30 Å

.

15. The method of claim 14, wherein a thickness of the second work function layer is 5 Å

to 50 Å

.

16-20. -20. (canceled)

21. A method comprising:

forming a first conductive layer over a first fin, the first conductive layer terminating closer to the first fin than a second fin;

forming a second conductive layer over the first conductive layer, the second conductive layer extending over the first fin and the second fin, the first conductive layer being interposed between the second conductive layer and the first fin; and

forming a metal layer over the first fin and the second fin.

22. The method of claim 21, further comprising forming a third conductive layer over the first conductive layer prior to forming the second conductive layer, the third conductive layer terminating closer to the second fin than the first fin.

23. The method of claim 21, further comprising:

prior to forming the first conductive layer, forming a dielectric layer, wherein the first fin and the second fin are exposed in a recess in the dielectric layer, wherein the first conductive layer extends along a sidewall of the recess.

24. The method of claim 23, further comprising planarizing the metal layer, wherein an upper surface of the dielectric layer is level with an upper surface of the metal layer after planarizing.

25. The method of claim 21, further comprising forming a gate dielectric prior to forming the first conductive layer, wherein the gate dielectric extends over the first fin and the second fin.