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STREAM PROCESSOR WITH HIGH BANDWIDTH AND LOW POWER VECTOR REGISTER FILE

  • US 20180357064A1
  • Filed: 07/07/2017
  • Published: 12/13/2018
  • Est. Priority Date: 06/09/2017
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a memory; and

    a processor coupled to the memory, wherein the processor comprises;

    a vector register file;

    a source operand buffer;

    a vector arithmetic logic unit (VALU); and

    a vector destination cache for storing results of instructions executed by the VALU;

    wherein the processor is configured to;

    evict a first cache line from the vector destination cache; and

    write the first cache line to the source operand buffer responsive to determining that the first cache line comprises one or more source operands targeted by a pending instruction.

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