STREAM PROCESSOR WITH HIGH BANDWIDTH AND LOW POWER VECTOR REGISTER FILE

• US 20180357064A1
• Filed: 07/07/2017
• Published: 12/13/2018
• Est. Priority Date: 06/09/2017
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chen, Jiasheng, He, Bin, Leather, Mark M., Mantor, Michael J., Zou, Yunxiao
• Granted Patent: US 10,817,302 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM'"'"'s output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

Claims

1. A system comprising:

a memory; and

a processor coupled to the memory, wherein the processor comprises;

a vector register file;

a source operand buffer;

a vector arithmetic logic unit (VALU); and

a vector destination cache for storing results of instructions executed by the VALU;

wherein the processor is configured to;

evict a first cache line from the vector destination cache; and

write the first cache line to the source operand buffer responsive to determining that the first cache line comprises one or more source operands targeted by a pending instruction.

2. The system as recited in claim 1, wherein the processor is further configured to:

identify one or more source operands of a first instruction;

determine whether to forward the one or more source operands from the vector register file, source operand buffer, or vector destination cache to the VALU;

wait until a last pipeline stage of the VALU until allocating a cache line in the vector destination cache; and

store a result of the first instruction in the cache line allocated in the vector destination cache.

3. The system as recited in claim 2, wherein the processor is configured to:

forward the one or more source operands from the source operand buffer responsive to determining the one or more source operands are stored in the source operand buffer;

prefetch the one or more source operands from the vector register file and store the one or more source operands in the source operand buffer responsive to determining the one or more source operands are stored in the vector register file; and

convey the one or more source operands from the source operand buffer to the VALU responsive to issuing the first instruction to the VALU.

4. The system as recited in claim 1, wherein the processor further comprises a plurality of flip-flops on outputs of the vector register file.

5. The system as recited in claim 4, wherein the vector register file comprises multiple banks, and wherein the processor is further configured to:

determine if a first operand matches a previous result on a given bank of the vector register file; and

bypass the source operand buffer to retrieve the first operand from flip-flops on the output of the given bank responsive to determining that the first operand matches the previous result on the given bank of the vector register file.

6. The system as recited in claim 1, wherein the processor is further configured to stall the VALU if the processor is unable to allocate a cache line in the vector destination cache.

7. The system as recited in claim 1, wherein the processor is configured to wait to allocate a cache line in the vector destination cache until a result is generated by the VALU.

8. A method comprising:

evicting a first cache line from the vector destination cache; and

writing the first cache line to the source operand buffer responsive to determining that the first cache line comprises one or more source operands targeted by a pending instruction.

9. The method as recited in claim 8, further comprising:

identifying one or more source operands of a first instruction;

determining whether to forward the one or more source operands from a vector register file, source operand buffer, or vector destination cache to a vector arithmetic logic unit (VALU) depending on one or more conditions;

waiting until a last pipeline stage of the VALU until allocating a cache line in the vector destination cache; and

storing a result of the first instruction in the cache line allocated in the vector destination cache.

10. The method as recited in claim 9, wherein:

forwarding the one or more source operands from the source operand buffer responsive to determining the one or more source operands are stored in the source operand buffer;

prefetching the one or more source operands from the vector register file and store the one or more source operands in the source operand buffer responsive to determining the one or more source operands are stored in the vector register file; and

conveying the one or more source operands from the source operand buffer to the VALU responsive to issuing the first instruction to the VALU.

11. The method as recited in claim 8, wherein a plurality of flip-flops are located on outputs of the vector register file.

12. The method as recited in claim 11, further comprising:

determining if a first operand matches a previous result on a given bank of the vector register file; and

bypassing the source operand buffer to retrieve the first operand from flip-flops on the output of the given bank responsive to determining that the first operand matches the previous result on the given bank of the vector register file.

13. The method as recited in claim 8, further comprising stalling the VALU responsive to being unable to allocate a cache line in the vector destination cache.

14. The method as recited in claim 8, further comprising waiting to allocate a cache line in the vector destination cache until a result is generated by the VALU.

15. An apparatus comprising:

a vector register file;

a source operand buffer;

a vector arithmetic logic unit (VALU); and

a vector destination cache for storing results of instructions executed by the VALU;

wherein the apparatus is configured to;

evict a first cache line from the vector destination cache; and

write the first cache line to the source operand buffer responsive to determining that the first cache line comprises one or more source operands targeted by a pending instruction.

16. The apparatus as recited in claim 15, wherein the apparatus is further configured to:

identify one or more source operands of a first instruction;

determine whether to forward the one or more source operands from the vector register file, source operand buffer, or vector destination cache to the VALU depending on one or more conditions;

wait until a last pipeline stage of the VALU until allocating a cache line in the vector destination cache; and

store a result of the first instruction in the cache line allocated in the vector destination cache.

17. The apparatus as recited in claim 16, wherein the apparatus is further configured to:

forward the one or more source operands from the source operand buffer responsive to determining the one or more source operands are stored in the source operand buffer;

prefetch the one or more source operands from the vector register file and store the one or more source operands in the source operand buffer responsive to determining the one or more source operands are stored in the vector register file; and

convey the one or more source operands from the source operand buffer to the VALU responsive to issuing the first instruction to the VALU.

18. The apparatus as recited in claim 15, wherein the apparatus further comprises a plurality of flip-flops on outputs of the vector register file.

19. The apparatus as recited in claim 18, wherein the vector register file comprises multiple banks, and wherein the apparatus is further configured to:

determine if a first operand matches a previous result on a given bank of the vector register file; and

bypass the source operand buffer to retrieve the first operand from flip-flops on the output of the given bank responsive to determining that the first operand matches the previous result on the given bank of the vector register file.

20. The apparatus as recited in claim 15, wherein the apparatus is further configured to stall the VALU if the apparatus is unable to allocate a cache line in the vector destination cache.