CELL PLACEMENT SITE OPTIMIZATION

• US 20180357351A1
• Filed: 01/29/2018
• Published: 12/13/2018
• Est. Priority Date: 06/07/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Yen-Hung, WANG, Chung-Hsing, HOU, Yuan-Te
• Granted Patent: US 10,642,949 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Abstract

The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Claims

1. A method for cell placement comprising:

partitioning a layout area into one or more contiguous units, wherein each unit comprises a plurality of placement sites;

mapping a first plurality of pin locations and a second plurality of pin locations to each of the one or more contiguous units, wherein each of the plurality of placement sites in each of the one or more contiguous units comprises a pin track from the first plurality of pin locations, a pin track from the second plurality of pin locations, or a combination thereof; and

placing a cell in the one or more contiguous units based on an allocation of one or more pins associated with the cell to at least one of the pin track from the first plurality of pin locations, the pin track from second plurality of pin locations, or a combination thereof, wherein the cell is retrieved from a cell library that comprises a plurality of pin locations for the cell.

2. The method of claim 1, wherein each of the one or more contiguous units comprises four placement sites S1-S4, and wherein the partitioning comprises arranging the placement site S1, the placement site S2, the placement site S3, and the placement site S4 in a contiguous manner.

3. The method of claim 2, wherein the mapping comprises:

mapping a first pin track from the first plurality of pin locations to the placement site S1;

mapping a second pin track from the second plurality of pin locations and a third pin track from the first plurality of pin locations to the placement site S2;

mapping a fourth pin track from the second plurality of pin locations to the placement site S3; and

mapping a fifth pin track from the first plurality of pin locations and a sixth pin track from the second plurality of pin locations to the placement site S4.

4. The method of claim 1, wherein the mapping comprises:

mapping the first plurality of pin locations to a first interconnect having a first electrical property, wherein the first interconnect is routed to electrically connect to at least one of the one or more pins associated with the cell; and

mapping the second plurality of pin locations to a second local interconnect having a second electrical property different from the first electrical property, wherein the second interconnect is routed to electrically connect to at least another one of the one or more pins associated with the cell.

5. The method of claim 4, wherein each of the first local interconnect and the second local interconnect comprises a metal M0 interconnect or a metal M1 interconnect.

6. The method of claim 1, wherein the cell library comprises a base cell library, a base cell library with a first pin offset, and a base cell library with a second pin offset, and wherein each of the base cell library, base cell library with a first pin offset, and base cell library with a second pin offset comprises the cell.

7. The method of claim 6, wherein the base cell library with a first pin offset comprises a first pin location for the cell, and wherein the first pin location comprises a placement site offset relative to a placement site of the cell as defined in the base cell library.

8. The method of claim 7, wherein the base cell library with a second pin offset comprises a second pin location for the cell, and wherein the second pin location comprises another placement site offset relative to the placement site of the cell as defined in the base cell library.

9. A computer system comprising:

a memory configured to store instructions; and

a processor, that when executing the instructions, is configured to perform operations comprising;

partitioning a layout area into one or more contiguous units, wherein each unit comprises a plurality of placement sites;

mapping a first plurality of pin locations and a second plurality of pin locations to each of the one or more contiguous units, wherein each of the plurality of placement sites in each of the one or more contiguous units comprises a pin track from the first plurality of pin locations, a pin track from the second plurality of pin locations, or a combination thereof; and

placing a cell in the one or more contiguous units based on an allocation of one or more pins associated with the cell to at least one of the pin track from the first plurality of pin locations, the pin track from second plurality of pin locations, or a combination thereof, wherein the cell is retrieved from a cell library that comprises a plurality of pin locations for the cell.

10. The computer system of claim 9, wherein each of the one or more contiguous units comprises four placement sites S1-S4, and wherein the partitioning comprises arranging the placement site S1, the placement site S2, the placement site S3, and the placement site S4 in a contiguous manner.

11. The computer system of claim 10, wherein the mapping comprises:

mapping a first pin track from the first plurality of pin locations to the placement site S1;

mapping a second pin track from the second plurality of pin locations and a third pin track from the first plurality of pin locations to the placement site S2;

mapping a fourth pin track from the second plurality of pin locations to the placement site S3; and

mapping a fifth pin track from the first plurality of pin locations and a sixth pin track from the second plurality of pin locations to the placement site S4.

12. The computer system of claim 9, wherein the cell library comprises a base cell library, a base cell library with a first pin offset, and a base cell library with a second pin offset, and wherein each of the base cell library, base cell library with a first pin offset, and base cell library with a second pin offset comprises the cell.

13. The computer system of claim 12, wherein the base cell library with a first pin offset comprises a first pin location for the cell, and wherein the first pin location comprises a placement site offset relative to a placement site of the cell as defined in the base cell library.

14. The computer system of claim 13, wherein the base cell library with a second pin offset comprises a second pin location for the cell, and wherein the second pin location comprises another placement site offset relative to the placement site of the cell as defined in the base cell library.

15. A non-transitory computer-readable medium having instructions stored thereon that, when executed by a computing device, causes the computing device to perform operations comprising:

partitioning a layout area into one or more contiguous units, wherein each unit comprises a plurality of placement sites;

mapping a first plurality of pin locations and a second plurality of pin locations to each of the one or more contiguous units, wherein each of the plurality of placement sites in each of the one or more contiguous units comprises a pin track from the first plurality of pin locations, a pin track from the second plurality of pin locations, or a combination thereof; and

placing a cell in the one or more contiguous units based on an allocation of one or more pins associated with the cell to at least one of the pin track from the first plurality of pin locations, the pin track from second plurality of pin locations, or a combination thereof, wherein the cell is retrieved from a cell library that comprises a plurality of pin locations for the cell.

16. The non-transitory computer-readable medium of claim 15, wherein the mapping comprises:

mapping the first plurality of pin locations to a first interconnect having a first electrical property, wherein the first interconnect is routed to electrically connect to at least one of the one or more pins associated with the cell; and

mapping the second plurality of pin locations to a second local interconnect having a second electrical property different from the first electrical property, wherein the second interconnect is routed to electrically connect to at least another one of the one or more pins associated with the cell.

17. The non-transitory computer-readable medium of claim 16, wherein each of the first local interconnect and the second local interconnect comprises a metal M0 interconnect or a metal M1 interconnect.

18. The non-transitory computer-readable medium of claim 16, wherein the cell library comprises a base cell library, a base cell library with a first pin offset, and a base cell library with a second pin offset, and wherein each of the base cell library, base cell library with a first pin offset, and base cell library with a second pin offset comprises the cell.

19. The non-transitory computer-readable medium of claim 18, wherein the base cell library with a first pin offset comprises a first pin location for the cell, and wherein the first pin location comprises a placement site offset relative to a placement site of the cell as defined in the base cell library.

20. The non-transitory computer-readable medium of claim 19, wherein the base cell library with a second pin offset comprises a second pin location for the cell, and wherein the second pin location comprises another placement site offset relative to the placement site of the cell as defined in the base cell library.