SELF-EVALUATING ARRAY OF MEMORY

• US 20180358110A1
• Filed: 06/13/2017
• Published: 12/13/2018
• Est. Priority Date: 06/13/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Buyuktosunoglu, Alper, Venkataramani, Swagath, Joshi, Rajiv, Swaminathan, Karthik V., Eldridge, Schuyler, Bose, Pradip
• Granted Patent: US 10,607,715 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Claims

1. A computer-implemented method comprising:

applying a first voltage to a memory in a neural network, wherein the memory includes one or more memory cells;

determining, by a processor, that a first memory cell in the memory is faulty at the first voltage, wherein the first voltage is a low voltage;

identifying a first factor in the neural network, wherein the first factor has a low criticality in the neural network;

determining to store the first factor in the first memory cell; and

storing the first factor in the first memory cell.

2. The method of claim 1, wherein determining to store the first factor in the first memory cell further comprises:

applying a second voltage to the memory in the neural network; and

determining that the first memory cell in the memory is faulty at the second voltage, wherein the second voltage is a high voltage.

3. The method of claim 1 further comprising:

determining that a second memory cell in the memory is not faulty at the first voltage;

identifying a second factor in the neural network, wherein the second factor has a high criticality in the neural network;

determining to store the second factor in the second memory cell; and

storing the second factor in the second memory cell.

4. The method of claim 3, wherein determining to store the second factor in the second memory cell further comprises:

applying a second voltage to the memory in the neural network; and

determining that the second memory cell in the memory is not faulty at the second voltage, wherein the second voltage is a high voltage.

5. The method of claim 4, further comprising:

determining that a third memory cell in the memory is not faulty at the first voltage;

determining that the third memory cell in the memory is faulty at the second voltage;

identifying a third factor in the neural network, wherein the third factor has a standard criticality in the neural network, wherein the standard criticality is below the high criticality and above the low criticality;

determining to store the third factor on the third memory cell; and

storing the third factor on the third memory cell.

6. The method of claim 4, further comprising:

determining that a third memory cell in the memory is faulty at the first voltage;

determining that the third memory cell in the memory is not faulty at the second voltage;

identifying a third factor in the neural network, wherein the third factor has a low criticality in the neural network;

determining to store the third factor on the third memory cell; and

storing the third factor on the third memory cell.

7. The method of claim 1, wherein the low voltage is a voltage below a predetermined threshold and wherein the first memory cell is determined to be faulty when the first memory cell does not transition a logic value at the low voltage.

8. The method of claim 2, wherein the high voltage is a voltage above a predetermined threshold.

9. The method of claim 1, further comprising:

applying a second voltage to all of the one or more memory cells included in the memory, wherein each of the one or more memory cells includes a logic value;

determining which memory cells of the one or more memory cells are faulty by identifying which memory cells do not transition the logic value to a second logic value at the second voltage;

determining which memory cells of the one or more memory cells are not faulty by identifying which memory cells do transition the logic value to the second logic value at the second voltage;

analyzing one or more factors in the neural network;

categorizing each factor as having the low criticality, a standard criticality, or a high criticality,

wherein the low criticality is determined by analyzing historical outputs of the neural network and identifying the factor as being below a first threshold,

wherein the standard criticality is determined by analyzing the historical outputs of the neural network and identifying the factor as being between the first threshold and a second threshold, and wherein the second threshold is higher than the first threshold, and

wherein the high criticality is determined by analyzing the historical outputs of the neural network and identifying the factor as being above the second threshold; and

assigning each factor to a specific memory cell of the one or more memory cells based on the criticality of the factor and the fault of the specific memory cell, wherein low criticality factors are assigned to faulty memory cells, and wherein standard criticality and high criticality factors are assigned to non-faulty memory cells.

10. A computer-implemented method comprising:

generating, by a processor, a first test pattern, wherein the first test pattern includes a first write operation at two or more voltages;

applying the first test pattern to a memory in a neural network, wherein the memory includes one or more memory cells, and wherein each memory cell attempts to perform the first write operation at each of the two or more voltages;

determining, in response to applying the first test pattern to the memory, that a first memory cell does not operate correctly at a first voltage; and

determining that the first memory cell operates correctly at a second voltage, wherein the second voltage is above the first voltage.

11. The method of claim 10, further comprising:

increasing the first voltage to the first memory cell, wherein the first voltage is increased to the second voltage;

maintaining the increased voltage to the first memory cell;

generating a second test pattern, wherein the second test pattern includes a second write at one or more voltages above the second voltage;

applying the second test pattern to the memory, wherein each memory cell in the memory attempts to perform the second write operation at each of the one or more voltages above the second voltage; and

determining, in response to applying the second test pattern to the memory, that each memory cell operates correctly at the one or more voltages above the second voltage.

12. The method of claim 10, wherein determining that the first memory cell does not operate correctly at the first voltage further comprises:

identifying that the first memory cell did not perform the first write operation at the first voltage.

13. The method of claim 10, wherein determining that the first memory cell operates correctly at the second voltage further comprises:

identifying that the first memory cell performed the first write operation at the second voltage.

14. The method of claim 11, wherein determining that each memory cell operates correctly at the one or more voltages above the second voltage further comprises:

identifying that each memory cell performed the second write operation at each of the one or more voltages above the second voltage.

15. The method of claim 11, further comprising:

identifying an amount of the two or more voltages that the first memory cell correctly operates;

comparing the amount to the total number of two or more voltages in the first test pattern;

determining, from the comparing, that the amount is below a threshold value for correctly operating;

identifying a lowest voltage of the two or more voltages at which the first memory cell correctly operates;

applying the lowest voltage to the first memory cell; and

maintaining the lowest voltage to the first memory cell during use of the memory in the neural network.

16. A system comprising:

a memory; and

a processor in communication with the memory, the processor being configured to perform operations comprising;

applying a first voltage to a memory in a neural network, wherein the memory includes one or more memory cells;

determining, by a processor, that a first memory cell in the memory is faulty at the first voltage, wherein the first voltage is a low voltage;

identifying a first factor in the neural network, wherein the first factor has a low criticality in the neural network;

determining to store the first factor in the first memory cell; and

storing the first factor in the first memory cell.

17. The system of claim 16 further comprising:

determining that a second memory cell in the memory is not faulty at the first voltage;

identifying a second factor in the neural network, wherein the second factor has a high criticality in the neural network;

determining to store the second factor in the second memory cell; and

storing the second factor in the second memory cell.

18. The system of claim 17, wherein determining to store the second factor in the second memory cell further comprises:

applying a second voltage to the memory in the neural network; and

determining that the second memory cell in the memory is not faulty at the second voltage, wherein the second voltage is a high voltage.

19. The system of claim 18, further comprising:

determining that a third memory cell in the memory is not faulty at the first voltage;

determining that the third memory cell in the memory is faulty at the second voltage;

identifying a third factor in the neural network, wherein the third factor has a standard criticality in the neural network, wherein the standard criticality is below the high criticality and above the low criticality;

determining to store the third factor on the third memory cell; and

storing the third factor on the third memory cell.

20. The system of claim 16, further comprising:

applying a second voltage to all of the one or more memory cells included in the memory, wherein each of the one or more memory cells includes a logic value;

determining which memory cells of the one or more memory cells are faulty by identifying which memory cells do not transition the logic value to a second logic value at the second voltage;

determining which memory cells of the one or more memory cells are not faulty by identifying which memory cells do transition the logic value to the second logic value at the second voltage;

analyzing one or more factors in the neural network;

categorizing each factor as having the low criticality, a standard criticality, or a high criticality,

wherein the low criticality is determined by analyzing historical outputs of the neural network and identifying the factor as being below a first threshold,

wherein the standard criticality is determined by analyzing the historical outputs of the neural network and identifying the factor as being between the first threshold and a second threshold, and wherein the second threshold is higher than the first threshold, and

wherein the high criticality is determined by analyzing the historical outputs of the neural network and identifying the factor as being above the second threshold; and

assigning each factor to a specific memory cell of the one or more memory cells based on the criticality of the factor and the fault of the specific memory cell, wherein low criticality factors are assigned to faulty memory cells, and wherein standard criticality and high criticality factors are assigned to non-faulty memory cells.