ENHANCEMENT-MODE/DEPLETION-MODE FIELD-EFFECT TRANSISTOR GAN TECHNOLOGY

• US 20180358357A1
• Filed: 06/07/2018
• Published: 12/13/2018
• Est. Priority Date: 06/08/2017
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Jimenez, Jose, Xie, Jinqiao
• Granted Patent: US 10,446,544 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

An integrated circuit die having a substrate with a first device stack disposed upon the substrate and a second device stack spaced from the first device stack and disposed upon the substrate is disclosed. The second device stack includes a first portion of a channel layer and a threshold voltage shift layer disposed between the first portion of the channel layer and the substrate, wherein the threshold voltage shift layer is configured to set a threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

Claims

1. An integrated circuit die comprising:

a substrate;

a first device stack disposed upon the substrate; and

a second device stack spaced from the first device stack and disposed upon the substrate, the second device stack comprising;

a first portion of a channel layer; and

a threshold voltage shift layer disposed between the first portion of the channel layer portion and the substrate, wherein the threshold voltage shift layer is configured to set a first threshold voltage that is a minimum device control voltage required to create a conducting path within the first portion of the channel layer.

2. The integrated circuit die of claim 1 wherein the first device stack comprises an enhancement-mode (E-mode) field-effect device and the second stack device comprises a depletion-mode (D-mode) field-effect device.

3. The integrated circuit die of claim 1 wherein the first device stack comprises a D-mode field-effect device and the second stack device comprises an E-mode field-effect device.

4. The integrated circuit die of claim 1 wherein the first threshold voltage is determined by a predetermined thickness of the threshold voltage shift layer.

5. The integrated circuit die of claim 4 wherein the predetermined thickness is within a range of thicknesses from 100 Å

to 300 Å

.

6. The integrated circuit die of claim 4 wherein the predetermined thickness is within a range of thicknesses from 300 Å

to 500 Å

.

7. The integrated circuit die of claim 1 wherein the first threshold voltage is determined by a predetermined dopant density within the threshold voltage shift layer.

8. The integrated circuit die of claim 7 wherein the predetermined dopant density is within a range of dopant densities from 1×

10¹⁷/cm³ to 3×

10¹⁷/cm³.

9. The integrated circuit die of claim 7 wherein the predetermined dopant density is within a range of dopant densities from 3×

10¹⁷/cm³ to 5×

10¹⁷/cm³.

10. The integrated circuit die of claim 1 wherein the first threshold voltage is determined by both a predetermined thickness of the threshold voltage shift layer and a predetermined dopant density of the threshold voltage shift layer.

11. The integrated circuit die of claim 1 wherein the first device stack and the second device stack are both gallium nitride based.

12. The integrated circuit die of claim 1 wherein the threshold voltage shift layer is made of a first semiconductor material having a first bandgap that is higher than a second bandgap of a second semiconductor material making up the channel layer.

13. The integrated circuit die of claim 1 wherein the second device stack has a second threshold voltage that is opposite in polarity from the first threshold voltage of the first device stack.

14. A method of fabricating an integrated circuit die comprising:

providing a substrate;

disposing a buffer layer over the substrate;

disposing a threshold voltage shift layer over the buffer layer to a predetermined thickness;

masking the threshold voltage shift layer with an etch mask to define a first device stack location;

etching through the threshold voltage shift layer not masked by the etch mask to create an exposed portion of the buffer layer;

removing the etch mask to expose a non-etched portion of the threshold voltage shift layer;

disposing a channel layer over the exposed portion of the buffer layer and the non-etched portion of the threshold voltage shift layer, wherein the threshold voltage shift layer is configured to set a first threshold voltage that is a minimum device control voltage required to create a conducting path within a portion of the channel layer residing over the non-etched portion of the threshold voltage shift layer.

15. The method of fabricating the integrated circuit die of claim 14 further comprising:

disposing a barrier layer over the channel layer;

forming an isolation region adjacent to the first device stack location to define a second device stack location spaced from the first device stack location;

disposing a first gate over the barrier layer at the first device stack location; and

disposing a second gate over the barrier layer at the second device stack location.

16. The method of fabricating the integrated circuit die of claim 15 further comprising:

disposing a first source over the channel layer at the first device stack location, wherein the first source is spaced from the first gate;

disposing a first drain over the channel layer at the first device stack location, wherein the first drain is spaced from both the first gate and the first source to realize a first field-effect device;

disposing a second source over the channel layer at the second device stack location, wherein the second source is spaced from the second gate; and

disposing a second drain over the channel layer at the second device stack location, wherein the second drain is spaced from both the second gate and the second source to realize a second field-effect device.

17. The method of fabricating the integrated circuit die of claim 15 wherein the first device stack comprises an enhancement-mode (E-mode) field-effect device and the second stack device comprises a depletion-mode (D-mode) field-effect device.

18. The method of fabricating the integrated circuit die of claim 15 wherein the first device stack comprises a D-mode field-effect device and the second stack device comprises an E-mode field-effect device.

19. The method of fabricating the integrated circuit die of claim 15 wherein the second device stack has a second threshold voltage that is opposite in polarity from the first threshold voltage of the first device stack.

20. The method of fabricating the integrated circuit die of claim 14 wherein the first threshold voltage is determined by a predetermined thickness of the threshold voltage shift layer.

21. The method of fabricating the integrated circuit die of claim 20 wherein the predetermined thickness is within a range of thicknesses from 100 Å

to 500 Å

.

22. The method of fabricating the integrated circuit die of claim 14 wherein the first threshold voltage is determined by a predetermined dopant density within the threshold voltage shift layer.

23. The method of fabricating the integrated circuit die of claim 22 wherein the predetermined dopant density is within a range of dopant densities from 1×

10¹⁷/cm³ to 5×

10¹⁷/cm³.

24. The method of fabricating the integrated circuit die of claim 14 wherein the threshold voltage shift layer is made of a first semiconductor material having a first bandgap that is higher than a second bandgap of a second semiconductor material making up the channel layer.

25. The method of fabricating the integrated circuit of claim 14 wherein the buffer layer is made of gallium nitride.