SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20180366483A1
• Filed: 12/21/2017
• Published: 12/20/2018
• Est. Priority Date: 06/16/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: CHOI, Kang Sik
• Granted Patent: US 10,418,372 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.

Claims

1. A semiconductor device, comprising:

a source select line including a first conductive layer and a second conductive layer disposed on the first conductive layer;

word lines stacked over the source select line while being spaced apart from one another;

a channel layer which passes through the word lines and the source select line and further protrudes toward a lower direction than the source select line; and

a source structure which is disposed under the source select line and is in direct contact with a lateral wall of the channel layer.

2. The semiconductor device of claim 1, wherein the source select line further includes an interface layer which is disposed between the first conductive layer and the second conductive layer and is formed of an insulating material.

3. The semiconductor device of claim 2, wherein an operation voltage applied to the source select line is applied to at least one of the first conductive layer and the second conductive layer, and induces coupling between the first conductive layer and the second conductive layer.

4. The semiconductor device of claim 1, wherein the source structure includes a first source layer, a second source layer, and a contact source layer disposed between the first source layer and the second source layer, and

the second source layer is disposed to be closer to the source select line than the first source layer.

5. The semiconductor device of claim 4, wherein the second source layer is formed to be thinner than the first conductive layer, the second conductive layer, and each of the word lines, and

the first conductive layer is formed to be thicker than the second conductive layer and each of the word lines.

6. The semiconductor device of claim 4, wherein each of the first source layer to the contact source layer is formed of a doped silicon layer including first conductive type impurities with a first concentration.

7. The semiconductor device of claim 6, wherein the first conductive type impurities include n-type impurities.

8. The semiconductor device of claim 4, wherein the first source layer is disposed to be farthest from the source select line than the second source layer and contact source layer.

9. The semiconductor device of claim 4, further comprising:

a first multilayer memory pattern and a second multilayer memory pattern which surround an exterior wall of the channel layer and are separated from each other by the contact source layer,

wherein the contact source layer is in contact with the lateral wall of the channel layer.

10. The semiconductor device of claim 1, further comprising:

a gate insulating layer disposed between the source structure and the first conductive layer;

an interface layer disposed between the first conductive layer and the second conductive layer; and

interlayer insulating layers disposed between the lowermost layer among the word lines and the second conductive layer and between the adjacent word lines,

wherein the interface layer is formed to be thinner than the gate insulating layer and each of the interlayer insulating layers.

11. The semiconductor device of claim 10, further comprising:

a first multilayer memory pattern and a second multilayer memory pattern which surround an exterior wall of the channel layer and are separated from each other by the source structure,

wherein the lateral wall of the channel layer disposed between the first and second multilayer memory patterns is in direct contact with a lateral wall of the source structure, and

a contact surface between the lateral wall of the channel layer and the lateral wall of the source structure is extended up to a height at which an interface of the gate insulating layer and the source structure is disposed.

12. The semiconductor device of claim 11, further comprising:

a source junction defined inside the channel layer,

wherein the source junction includes first conductive type impurities diffused into the channel layer from the contact surface and faces lateral walls of the first and second conductive layers.

13. The semiconductor device of claim 12, wherein the source junction is defined inside the channel layer that is surrounded by the second multilayer memory pattern and extends to the channel layer that is surrounded by the first multilayer memory pattern up to a height greater than that of the first conductive layer.

14. The semiconductor device of claim 1, wherein the second conductive layer and the word lines are formed of the same conductive material, and is formed of a conductive material having lower resistance than that of the first conductive layer.

15. The semiconductor device of claim 1, wherein the first conductive layer and the source structure are formed of doped silicon layers including first conductive type impurities.

16. The semiconductor device of claim 15, wherein the source structure includes the first conductive type impurities with a first concentration.

17. The semiconductor device of claim 16, further comprising:

a slit which passes through the word lines and the source select line and is extended into the source structure;

a first doping area which includes the first conductive type impurities with a second concentration higher than the first concentration, and is formed with a first thickness from a first surface of the source structure that is in contact with a bottom surface of the slit into the source structure; and

a source contact line which is in direct contact with the first doping area and is disposed inside the slit.

18. The semiconductor device of claim 17, further comprising:

a second doping area which includes the first conductive type impurities with a third concentration that is higher than the first concentration and is lower than the second concentration, and is formed with a second thickness from a second surface of the source structure that is in contact with a lateral wall of the slit into the source structure; and

a lateral wall insulating layer disposed between the source contact line and the lateral wall of the slit.