SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20180366488A1
• Filed: 01/09/2018
• Published: 12/20/2018
• Est. Priority Date: 06/16/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: CHOI, Kang Sik, LEE, Bong Hoon, LEE, Seung Cheol
• Granted Patent: US 10,263,010 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer;

a gate stack structure disposed on the second semiconductor layer;

a third semiconductor layer positioned between the first and second semiconductor layers; and

a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer;

wherein the third semiconductor layer is in contact with the channel pillar, and

wherein the third semiconductor layer includes a first protrusion protruding in an interface between the second semiconductor layer and the channel pillar.

2. The semiconductor device of claim 1, further comprising a first multilayer memory pattern surrounding the channel pillar, the first multilayer memory pattern having a bottom surface which is in contact with a top surface of the first protrusion of the third semiconductor layer.

3. The semiconductor device of claim 2, wherein the bottom surface of the first multilayer memory pattern is flat or horizontal.

4. The semiconductor device of claim 2, wherein the bottom surface of the first multilayer memory pattern has a negative slope in a direction from a sidewall of the channel pillar toward the gate stack structure.

5. The semiconductor device of claim 2, wherein the bottom surface of the first multilayer memory pattern has a convex polygonal line shape or a convex shape in a direction from the gate stack structure toward the first semiconductor layer.

6. The semiconductor device of claim 2, wherein the bottom surface of the first multilayer memory pattern has a height of from −

100 Å

to 20 Å

.

7. The semiconductor device of claim 2, wherein the bottom surface of the first multilayer memory pattern has a height of from −

50 Å

to about 20 Å

.

8. The semiconductor device of claim 2, wherein the first multilayer memory pattern includes a tunnel insulating layer, a data storage layer and a blocking insulating layer stacked in a sequential manner from the channel pillar toward the gate stack structure.

9. The semiconductor device of claim 1, wherein each of the first and third semiconductor layers includes a p-type dopant.

10. The semiconductor device of claim 1, wherein the second semiconductor layer is an undoped semiconductor layer, or includes a p-type dopant.

11. The semiconductor device of claim 1, further comprising:

a spacer insulating layer extending along sidewalls of the gate stack structure, the second semiconductor layer, and the third semiconductor layer; and

a source contact layer formed on the spacer insulating layer and contacting the first semiconductor layer.

12. The semiconductor device of claim 11, further comprising a source junction defined in the first to third semiconductor layers and disposed adjacent to the spacer insulating layer and the source contact layer.

13. The semiconductor device of claim 12, wherein each of the first and third semiconductor layers includes a dopant of a first conductivity type, and

the source junction includes a dopant of a second conductivity type different from the first conductivity type.

14. The semiconductor device of claim 12, wherein the source junction includes an n-type dopant.

15. The semiconductor device of claim 12, wherein the source junction comprises:

a first region including a dopant of a second conductivity type at a first concentration; and

a second region including the dopant of the second conductivity type at a second concentration greater than the first concentration.

16. The semiconductor device of claim 15, wherein the second region is defined in the first semiconductor layer to contact the source contact layer, and

the first region is defined in the first semiconductor layer adjacent to a sidewall of the second region and in the second and third semiconductor layers adjacent to a sidewall of the source contact layer.

17. The semiconductor device of claim 1, wherein the gate stack structure comprises:

a gate insulating layer contacting the second semiconductor layer; and

conductive patterns and interlayer insulating layers stacked alternately on the gate insulating layer,

wherein the gate insulating layer has a smaller thickness than the interlayer insulating layers.

18. The semiconductor device of claim 1, wherein the third semiconductor layer further comprises:

a second protrusion protruding between the first semiconductor layer and the channel pillar; and

a second multilayer memory pattern disposed between the first semiconductor layer and the channel pillar to surround the channel pillar.