3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof

• US 20180366489A1
• Filed: 06/19/2018
• Published: 12/20/2018
• Est. Priority Date: 06/20/2017
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli, Herner, Scott Brad, Chien, Wu-Yi
• Granted Patent: US 10,608,011 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface;

a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium;

a storage layer; and

a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent the storage layer and the conductors within the group.

2. The memory structure of claim 1, wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.

3. The memory structure of claim 1, further comprising a metallic layer contacting one of the second and the third semiconductor layer, wherein the metallic layer is provided in cavities or recesses that result from the removal of all or part of a sacrificial layer.

4. The memory structure of claim 1 wherein the sacrificial layer comprises one or more of:

silicon oxide, boron doped silicon oxide, phosphorus doped silicon oxide, boron phosphorus doped silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxygen hydrogen, germanium, and any combinations thereof.

5. The memory structure of claim 4 wherein the sacrificial layer is porous.

6. The memory structure of claim 3, wherein the metallic layer further comprises two or more sublayers where a first sublayer is disposed adjacent to and in electrical contact with a second sublayer, and the first sublayer surrounds the second sublayer on three or more sides.

7. The memory structure of claim 6 wherein the thickness of the second sublayer is at least 1.5×

the thickness of the first sublayer.

8. The memory structure of claim 3, wherein the metallic layer comprises one or more of:

titanium, titanium nitride, tungsten nitride, tungsten, titanium tungsten, tantalum, tantalum nitride, cobalt, chrome, molybdenum, niobium, and any alloys thereof.

9. The memory structure of claim 3, wherein the metallic layer is deposited by atomic layer deposition.

10. The memory structure of claim 1, further comprising a strut formed between two adjacent stacks of active strips, wherein the strut comprises an insulating layer physically connecting the adjacent stacks of active strips.

11. The memory structure of claim 10, wherein the strut is contact with and disposed to adjacent stacks of active strips at only a portion of the height of one of the stacks of active strips.

12. The memory structure of claim 11, wherein the struct connects adjacent stacks of active strips at the top of the stacks.

13. The memory structure of claim 10, wherein the strut is in contact with and disposed to adjacent stacks of active strips along substantially the entire height of the memory structure.

38. The memory structure of claim 1, wherein the storage layer in the memory structure comprises first and second types of storage material provided at different locations in the memory structure, the first and second types of storage material having different characteristics.

39. The memory structure of claim 38, wherein the first and second types of storage material comprise, respectively, first and second tunnel dielectric layers, the first tunnel dielectric layer being thicker than the second tunnel dielectric layer.

40. The memory structure of claim 38, wherein the first tunnel dielectric layer has a thickness of 5 nm or more.

41. The memory structure of claim 38, wherein the second tunnel dielectric layer has a thickness of 3 nm or less.

42. The memory structure of claim 38, wherein the storage layer comprises an oxide-nitride-oxide material.

14. A method for providing a memory structure, comprising:

providing a semiconductor substrate having a substantially planar surface;

providing a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium;

providing a storage layer; and

providing a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent storage layer and the conductors within the group.

15. The method of claim 14, wherein each active strip further comprises providing at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.

16. The method of claim 14, further comprising providing a metallic layer contacting one of the second and the third semiconductor layer, wherein the metallic layer is provided in cavities or recesses that result from the removal of all or part of a sacrificial layer.

17. The method of claim 14, wherein the sacrificial layer comprises one or more of:

silicon oxide, boron doped silicon oxide, phosphorus doped silicon oxide, boron phosphorus doped silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxygen hydrogen, germanium, and combinations thereof.

18. The method of claim 16, wherein the sacrificial layer is porous.

19. The method of claim 16, wherein the metallic layer further includes two or more sublayers where a first sublayer is disposed adjacent to and in electrical contact with a second sublayer, and the first sublayer surrounds the second sublayer on three or more sides.

20. The method of claim 19, wherein the thickness of the second sublayer is at least 1.5×

the thickness of the first sublayer.

21. The method of claim 16, wherein the metallic layer comprises one or more of:

titanium, titanium nitride, tungsten nitride, tungsten, titanium tungsten, tantalum, tantalum nitride, cobalt, chrome, molybdenum, or niobium, and any alloys thereof.

22. The method of claim 16, wherein the metallic layer is deposited by atomic layer deposition.

23. The method of claim 14, further comprising providing a strut between two adjacent stacks of active strips, wherein the strut comprises an insulating layer physically connecting the adjacent stacks of active strips.

24. The method of claim 23, wherein the strut is contact with and disposed to adjacent stacks of active strips at a portion of the height of one of the stacks of active strips.

25. The method of claim 23, wherein the struct connects the stacks of active strips at the top of the stacks.

26. The method of claim 23, wherein the strut is in contact with and disposed to adjacent stacks of active strips along substantially the entire height of the memory structure.

27. A memory structure, comprising:

a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry formed therein and thereon;

a first dielectric layer;

a first plurality of conductors electrically connected to the circuitry extending along a first direction substantially parallel to the planar surface, the conductors being accessible through the dielectric layer by a plurality of conductive plugs formed in vias to contact the conductors, the conductive plugs formed rows each extending along a second direction substantially parallel to the planar surface and substantially perpendicular to the first direction; and

a first stack of active strips and a second stack of active strips formed over dielectric layer and separated by a predetermined distance along the first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along the second direction, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type;

a storage layer;

a strut system connecting the first and second stacks of active strip; and

a second plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent the storage layer and the conductors within the group, wherein selected ones of the second plurality of conductors being connected by the conductive plugs to the first plurality of conductors.

28. The memory structure of claim 27, further comprising a third plurality of conductors electrically connected to the circuitry extending along the first direction, the conductors of the third direction being provided above the memory structure and being connected to the conductors of the second plurality that are not electrically connected to the first plurality of conductors through the conductive plugs.

29. The memory structure of claim 27, wherein struts including extensions that extend along the third direction through substantially the height of the stacks of active strips.

30. The memory structure of claim 27, further comprising a metallic layer contacting one of the second and the third semiconductor layer.

31. The memory structure of claim 27, wherein the metallic layer is provided in cavities or recesses that result from the removal of all or part of a sacrificial layer.

32. The memory structure of claim 30, wherein the sacrificial layer comprises one or more of:

silicon oxide, boron doped silicon oxide, phosphorus doped silicon oxide, boron phosphorus doped silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxygen hydrogen, germanium, and any combinations thereof.

33. The memory structure of claim 31, wherein the sacrificial layer is porous.

34. The memory structure of claim 30, wherein the metallic layer further includes two or more sublayers where a first sublayer is disposed adjacent to and in electrical contact with a second sublayer, and the first sublayer surrounds the second sublayer on three or more sides.

35. The memory structure of claim 34, wherein the thickness of the second sublayer is at least 1.5×

the thickness of the first sublayer.

36. The memory structure of claim 30, wherein the metallic layer comprises one or more of:

titanium, titanium nitride, tungsten nitride, tungsten, titanium tungsten, tantalum, tantalum nitride, cobalt, chrome, molybdenum, niobium, and any alloys thereof.

37. The memory structure of claim 30, wherein the metallic layer is deposited by atomic layer deposition.

43. The method of claim 27, wherein the storage layer in the memory structure comprises first and second types of storage material provided at different locations in the memory structure, the first and second types of storage material having different characteristics.

44. The method of claim 43, wherein the first and second types of storage material comprise, respectively, first and second tunnel dielectric layers, the first tunnel dielectric layer being thicker than the second tunnel dielectric layer.

45. The memory structure of claim 43, wherein the first tunnel dielectric layer has a thickness of 5 nm or more.

46. The memory structure of claim 43, wherein the second tunnel dielectric layer has a thickness of 3 nm or less.

47. The memory structure of claim 43, wherein the storage layer comprises an oxide-nitride-oxide material.

48. The memory structure of claim 27, wherein the storage layer in the memory structure comprises first and second types of storage material provided at different locations in the memory structure, the first and second types of storage material having different characteristics.

49. The memory structure of claim 48, wherein the first and second types of storage material comprise, respectively, first and second tunnel dielectric layers, the first tunnel dielectric layer being thicker than the second tunnel dielectric layer.

50. The memory structure of claim 48, wherein the first tunnel dielectric layer has a thickness of 5 nm or more.

51. The memory structure of claim 48, wherein the second tunnel dielectric layer has a thickness of 3 nm or less.

52. The memory structure of claim 48, wherein the storage layer comprises an oxide-nitride-oxide material.