Differential Circuit

• US 20180373363A1
• Filed: 08/29/2018
• Published: 12/27/2018
• Est. Priority Date: 01/24/2017
• Status: Active Grant

• Current Assignee: Shenzhen Goodix Technology Co., Ltd.
• Original Assignee: Shenzhen Goodix Technology Co., Ltd.
• Inventors: Hung, Tzu-Li, Yang, Fu-Chiang, Wen, Ya-Nan
• Granted Patent: US 10,642,430 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
• CPC Class Codes: H03F 3/45928 using IC blocks as the active amplifying circuit

Abstract

A differential circuit is provided. The differential circuit comprises a plurality of electrodes comprising at least a middle electrode, wherein the middle electrode is directly adjacent to a first electrode and a second electrode of the plurality of electrodes; a plurality of amplifiers, coupled to the plurality of electrodes; and at least a buffer, coupled between the middle electrode and at least one amplifier of the plurality of amplifiers.

Claims

1. A differential circuit, characterized in that, the differential circuit comprises:

a plurality of electrodes, comprising at least a middle electrode, wherein the middle electrode is directly adjacent to a first electrode and a second electrode of the plurality of electrodes;

a plurality of amplifiers, coupled to the plurality of electrodes; and

at least a buffer, coupled between the middle electrode and at least one amplifier of the plurality of amplifiers.

2. The differential circuit of claim 1, characterized in that, the middle electrode is coupled to a first amplifier and a second amplifier of the plurality of amplifiers.

3. The differential circuit of claim 2, characterized in that, the first amplifier comprises a first input terminal and a second input terminal, the second amplifier comprises a third input terminal and a fourth input terminal, the first input terminal is coupled to the first electrode, the fourth input terminal is coupled to the second electrode, the middle electrode is coupled to the second input terminal and the third input terminal.

4. The differential circuit of claim 3, characterized in that, the buffer is coupled between the middle electrode and the second input terminal of the first amplifier.

5. The differential circuit of claim 3, characterized in that, the buffer is coupled between the middle electrode and the third input terminal of the second amplifier.

6. The differential circuit of claim 1, characterized in that, further comprising:

a plurality of transconductance units, coupled between a plurality of input terminals of the plurality of amplifiers and the plurality of electrodes.

7. The differential circuit of claim 6, characterized in that, the transconductance unit comprises a resistor.

8. The differential circuit of claim 1, characterized in that, further comprising:

a transconductance unit, connected between the buffer and the at least one amplifier of the plurality of amplifiers.

9. The differential circuit of claim 1, characterized in that, further comprising:

a plurality of impedance units, coupled between a plurality of input terminals and a plurality of output terminals of the plurality of amplifiers.

10. The differential circuit of claim 9, characterized in that, the impedance unit comprises a resistor and a capacitor.

11. The differential circuit of claim 1, characterized in that, the amplifier comprises a full differential operation amplifier.