METHODS AND SYSTEMS FOR MANAGING DATA MIGRATION IN SOLID STATE NON-VOLATILE MEMORY

• US 20180373428A1
• Filed: 06/23/2017
• Published: 12/27/2018
• Est. Priority Date: 06/23/2017
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Kan, Lip Vui, Jang, Young Hwan
• Granted Patent: US 10,275,162 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Methods and systems that may be implemented for managing data migration from relatively higher performance and higher endurance solid state non-volatile memory media to relatively lower performance and lower endurance solid state non-volatile memory media. The disclosed methods and systems may be implemented to reduce write amplification that occurs to solid state non-volatile memory media of a memory device by using frequency of LBA update as a parameter for controlling and optimizing data eviction from a relatively higher performance and higher endurance input buffer section in the receiving front of a memory device to a relatively lower performance and lower endurance main memory section of the same memory device.

Claims

1. A memory device, comprising:

high endurance solid state memory having a first program-erase (P/E) cycle endurance level;

low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level;

at least one programmable integrated circuit programmed to control writing of incoming data to the memory device by;

writing all incoming data to data blocks in the high endurance solid state memory,

invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data,

determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory,

identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and

migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory.

2. The memory device of claim 1, further comprising non-volatile memory coupled to the at least one programmable integrated circuit for storing a mapping table and LBA write counter data;

where the the at least one programmable integrated circuit is programmed to access the mapping table to determine physical block addresses in the high endurance solid state memory corresponding to a LBA of the incoming data; and

to determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory in real time by incrementing a counter in the LBA write counter data corresponding to the LBA of the incoming data.

3. The memory device of claim 1, where the at least one programmable integrated circuit is further programmed to perform the step of migrating so as to evict the valid low frequency LBA update data to the data blocks of the low endurance solid state memory as part of a garbage collection operation for the memory device;

and to;

select valid low frequency LBA update data for eviction only from data blocks of the high endurance solid state memory that include more than a defined threshold level amount of invalid data; and

erase any given data block of the high endurance solid state memory only after all data in the given data block has been invalidated.

4. The memory device of claim 1, where the at least one programmable integrated circuit is further programmed to identify the high frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is greater than or equal to a defined high frequency data threshold value;

and to to identify the low frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is less than the defined high frequency data threshold.

5. The memory device of claim 4, where the at least one programmable integrated circuit is further programmed to monitor the amount of high frequency LBA update data contained in the the high endurance solid state memory;

and to;

lower the defined high frequency data threshold value when the monitored amount of high frequency LBA update data fills the high endurance solid state memory so as to reduce the amount of high frequency LBA update data contained in the the high endurance solid state memory; and

leave the defined high frequency data threshold value unchanged when the monitored amount of high frequency LBA update data does not fill the high endurance solid state memory.

6. The memory device of claim 1, where the at least one programmable integrated circuit is further programmed to:

identify valid medium frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is less than a LBA update frequency of the high frequency LBA update data and that is greater than a LBA update frequency of the low frequency LBA update data;

migrating the valid low frequency LBA update data from data blocks of the high endurance solid state memory only to a designated low frequency portion of the low endurance solid state memory media; and

migrating the valid medium frequency LBA update data from data blocks of the high endurance solid state memory only to a designated medium frequency portion of the low endurance solid state memory media that is a different portion of the the low endurance solid state memory media from the designated low frequency portion of the low endurance solid state memory media;

where the at least one programmable integrated circuit is further programmed to never migrate the valid low frequency LBA update data from data blocks of the high endurance solid state memory to the designated medium frequency portion of the low endurance solid state memory media, and to never migrate the valid medium frequency LBA update data from data blocks of the high endurance solid state memory to the designated low frequency portion of the low endurance solid state memory media.

7. The memory device of claim 1, where the high endurance solid state memory is single-level cell (SLC) NAND flash media having a single bit per cell;

and where the low endurance solid state memory is at least one of multi-level cell (MLC) memory having two bits per cell, triple-level cell (TLC) memory having three bits per cell, or quad-level cell (QLC) memory having four bits per cell.

8. An information handling system, comprising:

a host programmable integrated circuit;

a memory device coupled to receive incoming data from the host programmable integrated circuit, the memory device comprising;

high endurance solid state memory having a first program-erase (P/E) cycle endurance level,

low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level, and

at least one programmable integrated circuit;

where the at least one programmable integrated circuit of the memory device is programmed to control writing of incoming data to the memory device by;

writing all the incoming data to data blocks in the high endurance solid state memory,

invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data,

determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory,

identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and

migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory.

9. The system of claim 8, where the memory device further comprises non-volatile memory coupled to the at least one programmable integrated circuit of the memory device for storing a mapping table and LBA write counter data;

where the the at least one programmable integrated circuit of the memory device is programmed to access the mapping table to determine physical block addresses in the high endurance solid state memory corresponding to a LBA of the incoming data, and to determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory in real time by incrementing a counter in the LBA write counter data corresponding to the LBA of the incoming data.

10. The system of claim 8, where the at least one programmable integrated circuit of the memory device is further programmed to perform the step of migrating so as to evict the valid low frequency LBA update data to the data blocks of the low endurance solid state memory as part of a garbage collection operation for the memory device;

and to;

select valid low frequency LBA update data for eviction only from data blocks of the high endurance solid state memory that include more than a defined threshold level amount of invalid data; and

erase any given data block of the high endurance solid state memory only after all data in the given data block has been invalidated.

11. The system of claim 8, where the at least one programmable integrated circuit of the memory device is further programmed to identify the high frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is greater than or equal to a defined high frequency data threshold value;

and to to identify the low frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is less than the defined high frequency data threshold.

12. The system of claim 8, where the at least one programmable integrated circuit of the memory device is further programmed to:

identify valid medium frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is less than a LBA update frequency of the high frequency LBA update data and that is greater than a LBA update frequency of the low frequency LBA update data;

migrating the valid low frequency LBA update data from data blocks of the high endurance solid state memory only to a designated low frequency portion of the low endurance solid state memory media; and

migrating the valid medium frequency LBA update data from data blocks of the high endurance solid state memory only to a designated medium frequency portion of the low endurance solid state memory media that is a different portion of the the low endurance solid state memory media from the designated low frequency portion of the low endurance solid state memory media;

where the at least one programmable integrated circuit is further programmed to never migrate the valid low frequency LBA update data from data blocks of the high endurance solid state memory to the designated medium frequency portion of the low endurance solid state memory media, and to never migrate the valid medium frequency LBA update data from data blocks of the high endurance solid state memory to the designated low frequency portion of the low endurance solid state memory media.

13. The system of claim 8, where the at least one programmable integrated circuit is further programmed to migrate the valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory only while the host programmable integrated circuit is idle or during system idle time.

14. A method of operating a memory device comprising:

receiving incoming data in a memory device from a host programmable integrated circuit, the memory device comprising;

high endurance solid state memory having a first program-erase (P/E) cycle endurance level, and

low endurance solid state memory having a second program-erase (P/E) cycle endurance level that is less than the first program-erase (P/E) cycle endurance level; and

controlling writing of the incoming data to the memory device by;

writing all the incoming data to data blocks in the high endurance solid state memory,

invalidating existing data in the data blocks of the low endurance solid state memory and the high endurance solid state memory corresponding to a logical block address (LBA) as it is modified by the LBA of the incoming data,

determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory,

identifying valid high frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is greater than a LBA update frequency of other high frequency LBA update data in the data blocks of the high endurance solid state memory, and

migrating valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory that also contain invalidated data, and not migrating any valid high frequency LBA update data from the data blocks of the high endurance solid state memory to the data blocks of the low endurance solid state memory.

15. The method of claim 14, further comprising accessing a mapping table to determine physical block addresses in the high endurance solid state memory corresponding to a LBA of the incoming data, and determining a LBA update frequency of the valid data in the data blocks of the high endurance solid state memory in real time by incrementing a counter in the LBA write counter data corresponding to the LBA of the incoming data.

16. The method of claim 14, further comprising:

performing the step of migrating so as to evict the valid low frequency LBA update data to the data blocks of the low endurance solid state memory as part of a garbage collection operation for the memory device;

selecting valid low frequency LBA update data for eviction only from data blocks of the high endurance solid state memory that include more than a defined threshold level amount of invalid data; and

erasing any given data block of the high endurance solid state memory only after all data in the given data block has been invalidated.

17. The method of claim 14, further comprising identifying the high frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is greater than or equal to a defined high frequency data threshold value;

and identifying the low frequency LBA update data as valid data blocks of the high endurance solid state memory having a LBA update frequency that is less than the defined high frequency data threshold.

18. The method of claim 17, further comprising:

monitoring the amount of high frequency LBA update data contained in the the high endurance solid state memory;

lowering the defined high frequency data threshold value when the monitored amount of high frequency LBA update data fills the high endurance solid state memory so as to reduce the amount of high frequency LBA update data contained in the the high endurance solid state memory; and

leaving the defined high frequency data threshold value unchanged when the monitored amount of high frequency LBA update data does not fill the high endurance solid state memory.

19. The method of claim 14, further comprising:

identifying valid medium frequency LBA update data in the data blocks of the high endurance solid state memory that has a LBA update frequency that is less than a LBA update frequency of the high frequency LBA update data and that is greater than a LBA update frequency of the low frequency LBA update data;

migrating the valid low frequency LBA update data from data blocks of the high endurance solid state memory only to a designated low frequency portion of the low endurance solid state memory media; and

migrating the valid medium frequency LBA update data from data blocks of the high endurance solid state memory only to a designated medium frequency portion of the low endurance solid state memory media that is a different portion of the the low endurance solid state memory media from the designated low frequency portion of the low endurance solid state memory media;

never migrating the valid low frequency LBA update data from data blocks of the high endurance solid state memory to the designated medium frequency portion of the low endurance solid state memory media; and

never migrating the valid medium frequency LBA update data from data blocks of the high endurance solid state memory to the designated low frequency portion of the low endurance solid state memory media.

20. The method of claim 14, further comprising migrating the valid low frequency LBA update data to the data blocks of the low endurance solid state memory from data blocks of the high endurance solid state memory only while the host programmable integrated circuit is idle or during system idle time.