Semiconductor Device Including Wrap Around Contact and Method of Forming the Semiconductor Device

• US 20180374958A1
• Filed: 08/30/2018
• Published: 12/27/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guillorn, Michael A., Loubet, Nicolas Jean
• Granted Patent: US 10,615,281 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a plurality of semiconductor layers formed on a plurality of fin structures, an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, a gate structure formed on the plurality of semiconductor layers, and a wrap around contact formed on the epitaxial layer.

Claims

1. A semiconductor device, comprising:

a plurality of semiconductor layers formed on a plurality of fin structures;

an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

a gate structure formed on the plurality of semiconductor layers; and

a wrap around contact formed on the epitaxial layer.

2. The semiconductor device of claim 1, further comprising:

a shallow trench isolation (STI) region formed between the plurality of fin structures.

3. The semiconductor device of claim 2, wherein an upper surface of the STI region is coplanar with an upper surface of the plurality of fin structures.

4. The semiconductor device of claim 2, wherein the STI region comprises a plurality of shallow trench isolation (STI) regions formed between the plurality of fin structures, the wrap around contact being formed on the plurality of STI regions.

5. The semiconductor device of claim 1, wherein the gate structure comprises a metal layer and a spacer formed on a side of the metal layer.

6. The semiconductor device of claim 5, wherein the gate structure comprises a plurality of gate structures, and the wrap around contact is formed on the spacer and on the epitaxial layer between the plurality of gate structures.

7. The semiconductor device of claim 1, wherein the wrap around contact comprises a conformal metal liner layer, and a barrier layer formed on the metal liner layer.

8. The semiconductor device of claim 7, further comprising:

a metal fill layer formed on the barrier layer.

9. The semiconductor device of claim 1, wherein the epitaxial layer comprises a conformal highly-doped epitaxial film.

10. A semiconductor device, comprising:

a plurality of semiconductor layers formed on a plurality of fin structures;

a faceted epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

a gate structure formed on the plurality of semiconductor layers; and

a wrap around contact formed on the faceted epitaxial layer.

11. The semiconductor device of claim 10, further comprising:

a shallow trench isolation (STI) region formed between the plurality of fin structures.

12. The semiconductor device of claim 11, wherein an upper surface of the STI region is coplanar with an upper surface of the plurality of fin structures.

13. The semiconductor device of claim 11, wherein the STI region comprises a plurality of shallow trench isolation (STI) regions formed between the plurality of fin structures, the wrap around contact being formed on the plurality of STI regions.

14. The semiconductor device of claim 10, wherein the gate structure comprises a metal layer and a spacer formed on a side of the metal layer.

15. The semiconductor device of claim 14, wherein the gate structure comprises a plurality of gate structures, and the wrap around contact is formed on the spacer and on the epitaxial layer between the plurality of gate structures.

16. The semiconductor device of claim 10, wherein the wrap around contact comprises a conformal metal liner layer, and a barrier layer formed on the metal liner layer.

17. The semiconductor device of claim 16, further comprising:

a metal fill layer formed on the barrier layer.

18. The semiconductor device of claim 10, wherein the faceted epitaxial layer comprises a conformal highly-doped epitaxial film.

19. A semiconductor device, comprising:

a plurality of semiconductor layers formed on a plurality of fin structures;

a shallow trench isolation (STI) region formed between the plurality of fin structures, an upper surface of the STI region being coplanar with an upper surface of the plurality of fin structures;

an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

a plurality of gate structures formed on the plurality of semiconductor layers, and comprising a metal layer and a spacer formed on a side of the metal layer; and

a wrap around contact formed on the spacer and on the epitaxial layer between the plurality of gate structures.

20. The semiconductor device of claim 19, wherein the STI region comprises a plurality of shallow trench isolation (STI) regions formed between the plurality of fin structures, the wrap around contact being formed on the plurality of STI regions.