SYSTEM AND METHOD FOR SUPERCAPACITOR CHARGING AND BALANCING

• US 20180375345A1
• Filed: 06/22/2017
• Published: 12/27/2018
• Est. Priority Date: 06/22/2017
• Status: Active Grant

• Current Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Original Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Inventors: Altemose, George
• Granted Patent: US 10,374,440 B2
• Time in Patent Office: Days
• CPC Class Codes: H01G 11/00 Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
• CPC Class Codes: H01G 11/14 Arrangements or processes for adjusting or protecting hybrid or EDL capacitors emergency protective circuit arrangements specially adapted for capacitors, and effecting automatic switching in the event of an undesired change from normal working conditions H02H7/16; emergency protective circuit arrangements for limiting excess current or voltages without disconnection H02H9/00
• CPC Class Codes: H02J 2207/50 Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors
• CPC Class Codes: H02J 7/0014 Circuits for equalisation of charge between batteries
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02J 7/0019 using switched or multiplexed charge circuits
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: Y02E 60/13 Energy storage using capacitors

Abstract

In an illustrative embodiment, a supercapacitor system includes a common bus and a number of supercapacitor units, each of the supercapacitor units including one or more supercapacitors, coupled to the common bus via a balancing circuit, where each balancing circuit is configured to balance a charge of the one or more supercapacitors in the supercapacitor units by conducting current to supercapacitor units with a lower charge from supercapacitor units with a higher charge over the common bus, each balancing circuit including at least a first switch and a second switch, each switch controlled by a clock signal.

Claims

1. A supercapacitor system, comprising:

a common bus; and

a plurality of supercapacitor units, each of the plurality of supercapacitor units including one or more supercapacitors, coupled to the common bus via a balancing circuit, wherein

the balancing circuit is configured to balance a charge of the one or more supercapacitors in the plurality of supercapacitor units by conducting current to supercapacitor units with a lower charge from supercapacitor units with a higher charge over the common bus, and

the balancing circuit includes at least a first switch and a second switch, each switch controlled by a clock signal.

2. The supercapacitor system of claim 1, wherein the first switch and the second switch are MOSFET transistors.

3. The supercapacitor system of claim 1, wherein the first switch and the second switch are bipolar junction transistors.

4. The supercapacitor system of claim 1, wherein a phase of the clock signal for the first switch does not overlap a phase of the clock signal for the second switch.

5. The supercapacitor system of claim 1, wherein each balancing circuit of the plurality of supercapacitor units is capacitively coupled to the common bus.

6. The supercapacitor system of claim 1, wherein each balancing circuit of the plurality of supercapacitor units is coupled to the common bus via a transformer.

7. The supercapacitor system of claim 1, further comprising a charger power supply configured to supply charge to the plurality of supercapacitor units.

8. The supercapacitor system of claim 7, wherein the charger power supply has a maximum voltage equal to a rated voltage of the one or more supercapacitors in the plurality of supercapacitor units.

9. The supercapacitor system of claim 1, wherein the each of the plurality of supercapacitor units further includes a housing, the housing being configured to contain the one or more supercapacitors and the supercapacitor balancing circuit.

10. The supercapacitor system of claim 1, wherein the one or more supercapacitors in each of the plurality of supercapacitors are electrically coupled in parallel to form a virtual supercapacitor.

11. The supercapacitor system of claim 1, wherein all of the plurality of supercapacitor units are electrically coupled in series.

12. The supercapacitor system of claim 1, wherein each supercapacitor balancing circuit of plurality of supercapacitor units is configured to allow current to flow over the common bus from supercapacitor units with a higher charge to supercapacitor units with a lower charge until all of the supercapacitor units have the same charge.

13. A method for charging and balancing a plurality of supercapacitors units, the method comprising:

coupling a plurality of supercapacitor units to a common bus via a balancing circuit, each of the plurality of supercapacitor units including one or more supercapacitors; and

configuring each balancing circuit of the plurality of supercapacitor units to balance the charge of the plurality of supercapacitors units by conducting current to lower charge supercapacitors units from higher charge supercapacitors units over the common bus, each balancing circuit including at least a first switch and a second switch, each switch controlled by a clock signal.

14. The method of claim 13, wherein the first switch and the second switch are MOSFET transistors.

15. The method of claim 13, wherein the first switch and the second switch are bipolar junction transistors.

16. The method of claim 13, further comprising supplying charge from a charger power supply to the one or more supercapacitor units.

17. The method of claim 13, wherein a phase of the clock signal for the first switch does not overlap a phase of the clock signal for the second switch.

18. A supercapacitor charge balancing circuit comprising:

a supercapacitor having a first terminal and a second terminal;

a common bus;

a first switch having a first terminal electrically coupled to the first terminal of the supercapacitor, a second terminal electrically coupled to the common bus and a control terminal electrically coupled to a first clock signal;

a second switch having a first terminal electrically coupled to the common bus, a second terminal electrically coupled to the second terminal of the supercapacitor and a control terminal electrically coupled to a second clock signal; and

wherein a phase of the first clock signal does not overlap a phase of the second clock signal.

19. The supercapacitor balancing circuit of claim 18, wherein the first switch and the second switch are capacitively coupled to the common bus.

20. The supercapacitor balancing circuit of claim 18, wherein the first switch and the second switch are coupled to the common bus by a transformer.