PEAK-DELIVERED-POWER CIRCUIT FOR A VOLTAGE REGULATOR

• US 20180375433A1
• Filed: 06/23/2017
• Published: 12/27/2018
• Est. Priority Date: 06/23/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ahmed, Khondker, De, Vivek, Desai, Nachiket, Kim, Suhwan, Krishnamurthy, Harish, Liu, Xiaosen, Majumder, Turbo, Ravichandran, Krishnan, Schaef, Christopher, Vaidya, Vaibhav, Vangal, Sriram
• Granted Patent: US 10,530,254 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/67 to the maximum power available from a generator, e.g. from solar cell
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

Claims

1. A peak-delivered-power (PDP) controller, comprising:

memory to store a previous power output value and a new power output value, wherein the previous power output value and the new power output value correspond with power after a buck-boost power stage of a voltage regulator at a first time and a second time respectively;

measurement circuitry to measure an output voltage value and an output current value after the buck-boost power stage of the voltage regulator; and

control circuitry to;

calculate the new power output value after the buck-boost power stage from the output voltage value and the output current value;

determine whether the new power output value after the buck-boost power stage is greater than the previous power output value after the buck-boost power stage to determine whether the voltage regulator is outputting a maximum power output;

based on a determination that the new power output value after the buck-boost power stage is greater than the previous power output value after the buck-boost power stage, provide an instruction to a duty generator to increase a duty cycle of the voltage regulator;

based on a determination that the new power output value after the buck-boost power stage is not greater than the previous power output value after the buck-boost power stage, provide an instruction to the duty generator to decrease the duty cycle of the voltage regulator; and

replace the previous power output value with the new power output value.

2. The PDP controller of claim 1, wherein the measurement circuitry to measure the output voltage value and the output current value is further configured to receive the output voltage value and the output current value in a digital format.

3. The PDP controller of claim 2, wherein the measurement circuitry to receive the output voltage value and the output current value in the digital format is further configured to receive the output voltage value and the output current value from an analog-to-digital converter (ADC).

4. The PDP controller of claim 1, wherein the measurement circuitry to measure the output voltage value and the output current value is further configured to receive an output voltage and an output current in an analog format.

5. The PDP controller of claim 4, wherein the measurement circuitry to receive the output voltage and the output current is configured to receive the output voltage and the output current from one of a buck stage, a boost stage, and a buck-boost stage.

6. The PDP controller of claim 1, wherein the control circuitry to calculate the new power output value is further configured to multiply the output current value by the output voltage value to calculate the new power output value.

7. The PDP controller of claim 1, wherein a multiplication operation used to multiply the output current value by the output voltage value is an analog multiplication operation.

8. The PDP controller of claim 1, wherein a multiplication operation used to multiply the output current value by the output voltage value is a digital multiplication operation.

9. The PDP controller of claim 1, wherein the control circuitry is further to, based on replacing the previous power output value with the new power output value:

calculate the new power output value from a new output voltage value and a new output current value;

determine whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is currently outputting the maximum power output;

based on the determination that the new power output value is greater than the previous power output value, provide an indication to the duty generator to increase the duty cycle;

based on the determination that the new power output value is not greater than the previous power output value, provide the indication to the duty generator to decrease the duty cycle; and

replace the previous power output value with the new power output value.

10. A buck-boost regulator, comprising:

a buck-boost power stage to;

receive a voltage input and a current input; and

enable one of a buck mode and a boost mode to generate and provide an output voltage and an output current, from the voltage input and the current input, to an output capacitor;

a peak-delivered-power (PDP) controller to;

measure a power output value of the buck-boost power stage from the output voltage and the output current;

determine whether the power output value after the buck-boost power stage is greater than a previous power output value after the buck-boost power stage to determine whether a voltage regulator is outputting a maximum power output;

based on a determination that the power output value after the buck-boost power stage is greater than the previous power output value after the buck-boost power stage, provide a first instruction to a duty generator to increase a duty cycle; and

based on a determination that the power output value after the buck-boost power stage is not greater than the previous power output value after the buck-boost power stage, provide a second instruction to the duty generator to decrease the duty cycle; and

the duty generator to;

receive the first instruction and the second instruction;

based on receipt of the first instruction, increase the duty cycle of the buck-boost power stage by a first delta value; and

based on receipt of the second instruction, decrease the duty cycle of the buck-boost power stage by a second delta value.

11. The buck-boost regulator of claim 10, wherein the first delta value is a predetermined first delta value.

12. The buck-boost regulator of claim 11, wherein the duty generator to increase the duty cycle is further configured to increase the duty cycle by the first delta value that is constant.

13. The buck-boost regulator of claim 10, wherein the second delta value is a predetermined second delta value.

14. The buck-boost regulator of claim 13, wherein the duty generator to decrease the duty cycle is further configured to decrease the duty cycle by the second delta value that is constant.

15. The buck-boost regulator of claim 10, wherein the duty generator configured to increase the duty cycle is further configured to:

calculate the first delta value based on a difference between the power output value and the previous power output value.

16. The buck-boost regulator of claim 10, wherein the duty generator to decrease the duty cycle is further configured to:

calculate the second delta value based on a difference between the power output value and the previous power output value.

17. The buck-boost regulator of claim 10, further comprising an analog-to-digital converter to:

convert the output voltage and the output current from an analog format to a digital format to generate an output voltage value and an output current value; and

provide the output voltage value and the output current value in the digital format to the PDP controller.

18. A power system, comprising:

an energy transducer to generate a voltage input and a current input;

a buck-boost power stage to;

receive the voltage input and the current input; and

enable one of a buck mode and a boost mode to generate and provide an output voltage and an output current, from the voltage input and the current input, to a capacitor;

the capacitor to receive the output voltage and the output current;

a peak-delivered-power (PDP) controller to;

determine a power output value after the buck-boost power stage based on the output voltage and the output current of the buck-boost power stage; and

determine whether the power output value after the buck-boost power stage is greater than a previous power output value after the buck-boost power stage to determine whether a power output of the buck-boost power stage is a maximum power output of the buck-boost power stage; and

a duty generator to;

based on a determination that the power output value after the buck-boost power stage is greater than the previous power output value after the buck-boost power stage, increase a duty cycle of the buck-boost power stage by a first delta value; and

based on a determination that the power output value after the buck-boost power stage is not greater than the previous power output value after the buck-boost power stage, decrease the duty cycle of the buck-boost power stage by a second delta value.

19. The power system of claim 18, wherein the power output value of the buck-boost power stage is the power output value of the power system.

20. The power system of claim 18, wherein the PDP controller is further configured to configure the maximum power output of the buck-boost power stage regardless of an efficiency profile of the buck-boost power stage.