Clock Synchronization Device
First Claim
1. A clock synchronizing circuit comprising:
- a phase comparator comprising a first circuit having a first input configured to receive a data signal, the first circuit configured to detect edges of the data signal; and
a second circuit comprising a clock generator configured to generate a clock signal with adjustable frequency, wherein the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and wherein the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
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Accused Products
Abstract
In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
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Citations
22 Claims
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1. A clock synchronizing circuit comprising:
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a phase comparator comprising a first circuit having a first input configured to receive a data signal, the first circuit configured to detect edges of the data signal; and a second circuit comprising a clock generator configured to generate a clock signal with adjustable frequency, wherein the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and wherein the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of recovering a clock signal associated with a data signal, the method comprising:
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generating the clock signal; receiving the data signal at a clock input of a first flip-flop; detecting a first edge of the data signal; after detecting the first edge of the data signal, comparing an edge of the data signal with an edge of the clock signal; and modifying a frequency of the clock signal based on the comparing. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A circuit comprising:
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a clock generator configured to generate a clock signal; and a phase detector having an output coupled to the clock generator, the phase detector comprising a first flip-flop having a clock input configured to receive an asynchronous data signal, wherein the phase detector is configured to; detect a first edge of the asynchronous data signal, after detecting the first edge of the asynchronous data signal, compare an edge of the asynchronous data signal with an edge of the clock signal, and modify a frequency of the clock signal based on the comparison.
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Specification