ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD FOR ARITHMETIC PROCESSING DEVICE

• US 20190004795A1
• Filed: 06/22/2018
• Published: 01/03/2019
• Est. Priority Date: 07/03/2017
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kuramoto, Masahiro
• Granted Patent: US 10,713,042 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/06 Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent

Abstract

An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

Claims

1. An arithmetic processing device which overlaps second data having second element data included in a matrix on first data having first element data included in the matrix such that the first element data and the second element data are associated with each other, moves the second data in a row direction by a predetermined number of the first element data to perform a predetermined operation, and calculates third data having a matrix including third element data calculated by the predetermined operation in each state of overlapping of the second data on the first data, the arithmetic processing device comprising:

a memory configured to store the first data and the second data;

a plurality of arithmetic circuits;

a first memory arranged for each of the arithmetic circuits and configured to store a first predetermined row having the predetermined number of the first data stored in the memory;

a second memory arranged for each of the arithmetic circuits and configured to store a second predetermined row having a predetermined number of the second data stored in the memory; and

a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, wherein each of the multiply-add arithmetic circuits performs a processing of acquiring different first element data included in the first predetermined row from the first memory, acquiring the same second element data included in the second predetermined row from the second memory, and performing an operation using the acquired first element data and the acquired second element data a predetermined number of times, to obtain the third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

2. The arithmetic processing device according to claim 1, wherein each of the multiply-add arithmetic circuits performs a first operation of performing a process of acquiring different first element data included in the first predetermined row from the first memory, acquiring the same second element data included in the second predetermined row from the second memory, and multiplying the acquired first element data and the acquired second element data, by a number of columns of the third data, a second operation of performing a process of advancing an acquisition position of the first element data in the first predetermined row and an acquisition position of the second element data in the second predetermined row in the row direction by the predetermined number and performing the row operation by repeating the first operation by the number of columns of the third data, while advancing the first predetermined row and the second predetermined row, row by row, by a number of rows of the second data, and a third operation of repeating the second operation while advancing the first predetermined row and the second predetermined row in a column direction by the predetermined number, and calculates the third element data based on an operation result of the third operation to obtain the third data.

3. The arithmetic processing device according to claim 1, wherein a number of arithmetic circuits corresponds to a number of columns of the third data.

4. A control method for an arithmetic processing device which overlaps second data having second element data included in a matrix on first data having first element data included in the matrix such that the first element data and the second element data are associated with each other, moves the second data in a row direction by a predetermined number of the first element data to perform a predetermined operation, and calculates third data having a matrix including third element data calculated by the predetermined operation in each state of overlapping of the second data on the first data, the control method comprising:

storing the first data and the second data in a memory;

storing a first predetermined row having the predetermined number of the first data stored in the memory in a first memory;

storing a second predetermined row having a predetermined number of the second data stored in the memory in a second memory;

acquiring different first element data included in the first predetermined row from the first memory;

acquiring the same second element data included in the second predetermined row from the second memory;

performing an operation using the acquired first element data and the acquired second element data a predetermined number of times; and

obtaining the third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.