PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH SECURITY, POWER REDUCTION, AND PERFORMACE FEATURES

• US 20190004878A1
• Filed: 07/01/2017
• Published: 01/03/2019
• Est. Priority Date: 07/01/2017
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Adler, Michael C., Fleming, Kermin, Glossop, Kent D., Steely, JR., Simon C.
• Application Number:
  US15/640,542
• Publication Number:
  US 20190004878A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 21/629 to features or functions of an application
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/81 by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/543 User-generated data transfer, e.g. clipboards, dynamic data exchange [DDE], object linking and embedding [OLE]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of two dataflow graphs each comprising a plurality of nodes, wherein a first dataflow graph and a second dataflow graph are be overlaid into a first and second portion, respectively, of the interconnect network and a first and second subset, respectively, of the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the first and second subsets of the plurality of processing elements are to perform a first and second operation, respectively, when incoming first and second, respectively, operand sets arrive at the plurality of processing elements.

Claims

1. A processor comprising:

a plurality of processing elements; and

an interconnect network between the plurality of processing elements to receive a first input of a first dataflow graph comprising a first plurality of nodes, wherein the first dataflow graph is to be overlaid into a first portion of the interconnect network and a first subset of the plurality of processing elements with each of the first plurality of nodes represented as a dataflow operator in the first subset of the plurality of processing elements, and the first subset of the plurality of processing elements is to perform a first operation when a first incoming operand set arrives at the first subset of the plurality of processing elements;

the interconnect network also to receive a second input of a second dataflow graph comprising a second plurality of nodes, wherein the second dataflow graph is to be overlaid into a second portion the interconnect network and a second subset of the plurality of processing elements with each of the second plurality of nodes represented as a dataflow operator in the second subset of the plurality of processing elements, and the second subset of the plurality of processing elements is to perform a second operation when a second incoming operand set arrives at the second subset of the plurality of processing elements.

2. The processor of claim 1, wherein the first subset of the plurality of processing elements is assigned to a first program and the second subset of the plurality of processing elements is assigned to a second program.

3. The processor of claim 2, wherein the interconnect network is to be partitioned into the first portion and the second portion to protect the first program and the second program from each other.

4. The processor of claim 3, wherein the first program is a user-level program.

5. The processor of claim 4, wherein the second program is a system-level program.

6. The processor of claim 4, wherein the second program is a user-level program.

7. The processor of claim 3, wherein the first program and the second program are to be protected from each other by a boundary to be implemented with configurable privileged state elements.

8. The processor of claim 7, wherein the configurable privileged state elements are to be configured to prevent communication across the boundary.

9. A method comprising:

partitioning, into a first portion and a second portion, a plurality of processing elements of a processor and an interconnect network between the plurality of processing elements;

receiving a first input of a first dataflow graph comprising a first plurality of nodes;

overlaying the first dataflow graph into the first portion with each of the first plurality of nodes represented as a dataflow operator in a first subset of the plurality of processing elements;

receiving a second input of a second dataflow graph comprising a second plurality of nodes;

overlaying the second dataflow graph into the second portion with each of the second plurality of nodes represented as a dataflow operator in a second subset of the plurality of processing elements;

performing a first operation of the first dataflow graph with the first portion of the interconnect network and the first subset of the plurality of processing elements when a first incoming operand set arrives at the first subset of the plurality of processing elements; and

performing a second operation of the second dataflow graph with the second portion of the interconnect network and the second subset of the plurality of processing elements when a second incoming operand set arrives at the second subset of the plurality of processing elements.

10. The method of claim 9, further comprising:

assigning a first program to the first subset of the plurality of processing elements; and

assigning a second program to the second subset of the plurality of processing elements.

11. The method of claim 10, wherein the interconnect network is partitioned into the first portion and the second portion to protect the first program and the second program from each other.

12. The method of claim 11, wherein the first program is a user-level program.

13. The method of claim 12, wherein the second program is a system-level program.

14. The method of claim 12, wherein the second program is a user-level program.

15. The method of claim 11, wherein the first program and the second program are protected from each other by a boundary to be implemented with configurable privileged state elements.

16. The method of claim 15, wherein partitioning includes configuring the configurable privileged state elements to prevent communication across the boundary.

17. A non-transitory machine-readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

partitioning, into a first portion and a second portion, a plurality of processing elements of a processor and an interconnect network between the plurality of processing elements;

receiving a first input of a first dataflow graph comprising a first plurality of nodes;

overlaying the first dataflow graph into the first portion with each of the first plurality of nodes represented as a dataflow operator in a first subset of the plurality of processing elements;

receiving a second input of a second dataflow graph comprising a second plurality of nodes;

overlaying the second dataflow graph into the second portion with each of the second plurality of nodes represented as a dataflow operator in a second subset of the plurality of processing elements;

performing a first operation of the first dataflow graph with the first portion of the interconnect network and the first subset of the plurality of processing elements when a first incoming operand set arrives at the first subset of the plurality of processing elements; and

performing a second operation of the second dataflow graph with the second portion of the interconnect network and the second subset of the plurality of processing elements when a second incoming operand set arrives at the second subset of the plurality of processing elements.

18. The non-transitory machine-readable medium of claim 17, wherein the method further comprises:

assigning a first program to the first subset of the plurality of processing elements; and

assigning a second program to the second subset of the plurality of processing elements.

19. The non-transitory machine-readable medium of claim 18, wherein the first program and the second program are protected from each other by a boundary implemented with configurable privileged state elements.

20. The non-transitory machine-readable medium of claim 19, wherein partitioning includes configuring the configurable privileged state elements to prevent communication across the boundary.