HEAP MANAGEMENT FOR MEMORY CORRUPTION DETECTION

• US 20190004886A1
• Filed: 09/06/2018
• Published: 01/03/2019
• Est. Priority Date: 03/02/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stark, Tomer, Tal, Ady, Gabor, Ron
• Granted Patent: US 10,585,741 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.

Claims

1. A processor, comprising:

a memory to store data from an application and a metadata table that stores a first metadata value associated with a first set of one or more contiguous memory blocks of the memory and a second metadata value associated with a second set of one or more contiguous memory blocks of the memory; and

a processor core coupled to the memory, wherein the processing core is to;

receive a first pointer produced by a first memory access instruction of the application being executed by the processor, the first pointer comprising a first memory address of a first memory object and a third metadata value, the memory address identifying a memory block in the first set of one or more contiguous memory blocks;

compare the third metadata value to the first metadata value; and

communicate a memory corruption detection message to the application when the third metadata value does not match the first metadata value.

2. The processor of claim 1, wherein the first metadata value is a first unique identifier associated with the first set of one or more contiguous memory blocks, and wherein the second metadata value is a second unique identifier associated with the second set of one or more contiguous memory blocks.

3. The processor of claim 2, wherein the processor core is to:

receive, from the application, an allocation request for an allocation of the first set of one or more contiguous memory blocks of the memory for the memory object;

allocate the first set of one or more contiguous memory blocks for the first memory object in view of a size of the first memory object requested;

write, into the metadata table, the first unique identifier;

create a pointer with the memory address of the memory object and the first unique identifier associated with the memory object; and

provide, to the application, the pointer with the first unique identifier.

4. The processor of claim 3, wherein the allocation request is for an allocation having at least one of a first size or a second size, wherein the first size corresponds to a number of contiguous memory blocks below a first threshold amount, and wherein the second size corresponds to a number of contiguous memory blocks that exceeds the first threshold amount.

5. The processor of claim 3, wherein the processor core is to:

receive a second pointer produced by a second memory access instruction of the application being executed by the processor, the second pointer comprising a second memory address of a second object and a fourth metadata value, the second memory address identifying a memory block in the second set of one or more contiguous memory blocks;

compare the fourth metadata value to the second unique identifier; and

communicate the second object to the application when the fourth metadata value matches the second unique identifier.

6. The processor of claim 3, wherein the processor core is further to determine the size of the first memory object requested by the allocation request, and wherein the first set of one or more contiguous memory blocks is allocated as a first allocated buffer and the second set of one or more contiguous memory blocks is allocated as a second allocated buffer.

7. The processor of claim 3, wherein the size of the first memory object requested is at least one of a first size, a second size, or a third size, wherein the first size corresponds to a number of contiguous memory blocks below a first threshold amount, wherein the second size corresponds to a number of contiguous memory blocks that exceeds the first threshold amount and is below a second threshold amount, and wherein the third size corresponds to a number of contiguous memory blocks that exceeds the second threshold amount.

8. A processor comprising:

a memory to store a data structure; and

a processor core coupled to the memory, wherein the processing core is to;

receive a request from an application, the request specifying at least one of a first size or a second size of a memory object, wherein the first size corresponds to a number of contiguous memory blocks below a first threshold amount, and wherein the second size corresponds to a number of contiguous memory blocks that exceeds the first threshold amount;

write, into the data structure, a first unique identifier associated with one or more contiguous memory blocks of the memory;

create a pointer with a memory address of the memory object and a second unique identifier associated with the memory object; and

provide the pointer to the application.

9. The processor of claim 8, wherein the processing core is further to:

receive, from the application, an allocation request for an allocation of the one or more contiguous memory blocks of the memory for the memory object; and

allocate the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested.

10. The processor of claim 8, wherein the processing core is further to:

divide the one or more contiguous memory blocks into a plurality of sub-blocks, wherein the plurality of sub-blocks comprise;

an initial sub-block;

one or more middle sub-blocks; and

a last sub-block; and

store data in at least one of a memory allocation meta-data field, a user data field, an overhead data field, or an empty data field, wherein each of the least one of the memory allocation meta-data field, the user data field, the overhead data field, or the empty data field is aligned at a boundary of one of the plurality of sub-blocks.

11. The processor of claim 10, wherein the processor core is further to:

store memory allocation information of the data in the memory allocation meta-data field within initial sub-block so that the memory allocation meta-data field is aligned with a starting boundary of the initial block;

store user information of the data in the user data field within a first middle sub-block of the one or more middle sub-blocks so that the user data field is aligned with a starting boundary of the first middle sub-block; and

store overhead information of the data in the overhead data field with the last sub-block of the last sub-block so that the overhead data field is aligned with an ending boundary of the last sub-block.

12. The processor of claim 10, wherein the processor core is further to:

store no data in the empty data field within initial sub-block, wherein the empty data field is aligned with a starting boundary of the initial block;

store memory allocation information of the data in the memory allocation meta-data field within a first middle sub-block of the one or more middle sub-blocks so that the memory allocation meta-data field is aligned with a starting boundary of the first middle sub-block;

store user information of the data in the user data field within a second middle sub-block of the one or more middle sub-blocks so that the user data field is aligned with a starting boundary of the second middle sub-block; and

store overhead information of the data in the overhead data field with the last sub-block of the last sub-block so that the overhead data field is aligned with an ending boundary of the last sub-block.

12-1. The processor of claim 10, wherein the processor core is further to:

store memory allocation information of the data in the memory allocation meta-data field within initial sub-block so that the memory allocation meta-data field is aligned with a starting boundary of the initial block;

store overhead information of the data in the overhead data field within a first middle sub-block of the one or more middle sub-blocks so that the overhead data field is aligned with a starting boundary of the first middle sub-block; and

store user information of the data in the user data field with the last sub-block of the last sub-block so that the user data field is aligned with an ending boundary of the last sub-block.

13. The processor of claim 10, wherein the processor core is further to store memory allocation information of the data in the memory allocation meta-data field, user information of the data in the user data field, overhead information of the data in the overhead data field, or no data in the empty data field based on a predetermined sub-block alignment of the processor.

14. The processor of claim 8, wherein the processor is further to determine the first unique identifier associated with the memory object using a round-robin selection scheme.

15. A processor comprising:

a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) data structure; and

a processor core coupled to the memory, wherein the processing core is to;

receive, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object;

allocate the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested;

write, into the MCD data structure, a first MCD designation associated with the one or more contiguous memory blocks;

create a pointer with a memory address of the memory object and a second MCD designation associated with the memory object;

send, to the application, the pointer;

determine the first MCD designation associated with the memory object using a random selection scheme; and

verify that the first MCD designation is different from another MCD designation of an adjacent contiguous memory block.

16. A system comprising:

a processor;

a memory device coupled to the processor, the memory device to store a memory corruption detection (MCD) data structure; and

a memory controller coupled to the memory device, the memory controller to;

receive, from an application, a release request for a release of a memory object in a system memory of a processor, wherein the release request comprises a pointer;

identify a first unique identifier and a memory address of the pointer;

change the first unique identifier, stored in the MCD data structure, to a second unique identifier for the memory address; and

release a memory object in the system memory associated with the memory address.

17. The system of claim 16, wherein the memory controller is further to change, by the processor, the first unique identifier to the second unique identifier using a round-robin selection scheme.

18. The system of claim 16, wherein the memory controller is further to change, by the processor, the first unique identifier to the second unique identifier using a random selection scheme.

19. The system of claim 16, wherein the memory controller is further to verify, by the processor, that the second unique identifier is different than another unique identifier of an adjacent contiguous memory block.

20. The system of claim 16, wherein the second unique identifier is a predefined unique identifier.