PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH TRANSACTIONAL AND REPLAY FEATURES

• US 20190004945A1
• Filed: 07/01/2017
• Published: 01/03/2019
• Est. Priority Date: 07/01/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fleming, Kermin, Glossop, Kent D., Steely, JR., Simon C., Sury, Samantika S.
• Granted Patent: US 10,445,234 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 15/825 Dataflow computers
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.

Claims

1. (canceled)

2. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a transaction controller to group a plurality of memory accesses associated with the operation.

3. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a transaction controller to group a plurality of memory accesses associated with the operation, wherein the transaction controller is to group the plurality of memory accesses into a transaction, by marking, with a transaction identifier, a cache line to be modified by the operation.

4. The processor of claim 3, wherein a first message is to be sent to the transaction controller in connection with a beginning of the transaction.

5. The processor of claim 4, wherein a second message is to be sent to the transaction controller in connection with an end of the transaction.

6. The processor of claim 5, wherein the transaction controller is to clear the transaction identifier from the cache line in response to the second message.

7. The processor of claim 3, wherein the plurality of memory accesses includes a read by a first of the plurality of processing elements.

8. The processor of claim 7, wherein the plurality of memory accesses includes a write by a second of the plurality of processing elements.

9. The processor of claim 8, wherein the first and the second of the plurality of processing elements are different processing elements.

10. The processor of claim 8, wherein the first and the second of the plurality of processing elements are the same processing element.

11. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a cache, the cache to be included in a memory subsystem, the memory subsystem also to include a memory in which to store a plurality of old data values to replay execution from start of an epoch, the epoch to include the operation.

12. The processor of claim 11, wherein a first of the plurality of old data values is to be preserved, until end of the epoch, in the memory in response to a corresponding new data value being stored in a line of the cache by one of the plurality of processing elements.

13. The processor of claim 12, wherein the new data value is from a write from one of the plurality of processing elements.

14. The processor of claim 13, wherein the first of the plurality of old data values is to be preserved according to a cache coherency protocol.

15. A method comprising:

receiving an input of a dataflow graph comprising a plurality of nodes;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements;

performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements when an incoming operand set arrives the plurality of processing elements; and

preserving a plurality of old data values in a memory during an epoch, the epoch including writing a new data value from one of the plurality of processing elements, the new value corresponding one of the plurality of old data values.

16. The method of claim 15, further comprising obtaining, by a cache according to a cache coherency protocol, ownership of a cache line in which to store the new data value.

17. The method of claim 16, further comprising, in response to determining that the cache line is coherently owned by the cache, writing the cache line to the memory.

18. The method of claim 17, further comprising updating the cache line to the new value after writing the cache line to the memory.

19. The method of claim 18, further comprising changing the cache line from coherently owned to speculatively owned after writing the cache line to the memory.

20. The method of claim 16, further comprising, in response to determining that the cache line is speculatively owned by the cache, updating the cache line to the new value without writing the line to the memory.