PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH MEMORY SYSTEM PERFORMANCE, POWER REDUCTION, AND ATOMICS SUPPORT FEATURES

• US 20190004955A1
• Filed: 07/01/2017
• Published: 01/03/2019
• Est. Priority Date: 07/01/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Adler, Michael C., Chou, Chiachen, Crago, Neal C., Fleming, Kermin, Glossop, Kent D., Jaleel, Aamer, Marolia, Pratik M., Steely, JR., Simon C., Sury, Samantika S.
• Granted Patent: US 10,387,319 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

Claims

1. A processor comprising:

a plurality of processing elements;

an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and

a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

2. The processor of claim 1, wherein the streamer element is to prefetch based on a programmable memory access pattern.

3. The processor of claim 2, wherein the streamer element includes a plurality of tracking registers to fetch ahead of a demand stream.

4. The processor of claim 3, wherein the plurality of tracking registers includes an x-dimension register to fetch ahead in a first dimension of a multidimensional streaming fetch pattern.

5. The processor of claim 4, wherein the plurality of tracking registers includes a y-dimension register to fetch ahead in a second dimension of the multidimensional streaming fetch pattern.

6-10. -10. (canceled)

11. A method comprising:

receiving an input of a dataflow graph comprising a plurality of nodes;

overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements;

prefetching, by a streamer element, an incoming operand set from two or more levels of a memory system; and

performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements when the incoming operand set arrives at the plurality of processing elements.

12. The method of claim 11, wherein the streamer element is to prefetch based on a programmable memory access pattern.

13. The method of claim 12, wherein the streamer element includes a plurality of tracking registers to fetch ahead of a demand stream.

14. The method of claim 13, wherein the plurality of tracking registers includes an x-dimension register to fetch ahead in a first dimension of a multidimensional streaming fetch pattern.

15. The method of claim 14, wherein the plurality of tracking registers includes a y-dimension register to fetch ahead in a second dimension of the multidimensional streaming fetch pattern.

16-20. -20. (canceled)