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CIRCUIT FOR CMOS BASED RESISTIVE PROCESSING UNIT

  • US 20190005382A1
  • Filed: 11/21/2017
  • Published: 01/03/2019
  • Est. Priority Date: 06/30/2017
  • Status: Active Grant
First Claim
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1. A method of operating a resistive processing unit of a neural network, said method comprising:

  • storing a charge on a complementary-metal-oxide semiconductor (CMOS) capacitor device, said charge representing a weight value associated with a neural network circuit operation;

    receiving at a first analog processing circuit a first analog voltage signal;

    receiving at a second analog processing circuit a second analog voltage signal;

    inputting at said first analog processing circuit a pulse signal of pre-determined pulse width during said neural network circuit operation,generating, from said input pulse signal, a further pulsed signal for input to said second analog processing circuit;

    generating a first analog output signal at said first analog processing circuit, andgenerating a second analog output signal at said second analog processing circuit, said first analog and second analog output signals of values for controlling a charging circuit operatively connected to said capacitor device and a discharging circuit operatively connected to said capacitor device to respectively increase a charge stored on said capacitor device, or decrease a charge stored on said capacitor device.

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