PIXEL CIRCUIT, ARRAY SUBSTRATE, DISPLAY DEVICE AND CONTROLLING METHOD THEREOF

• US 20190005868A1
• Filed: 08/03/2017
• Published: 01/03/2019
• Est. Priority Date: 01/03/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: XIAO, Li, LIU, Dongni, CHEN, Xiaochuan, YANG, Shengji, WANG, Lei, LU, Pengcheng, FU, Jie, YUE, Han
• Granted Patent: US 10,643,520 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/013 Eye tracking input arrangements G06F3/015 takes precedence
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0871 with level shifting
• CPC Class Codes: G09G 2310/0213 controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• CPC Class Codes: G09G 2310/0243 Details of the generation of driving signals
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

Embodiments of the present disclosure provide a pixel circuit, an array substrate, a display device and a controlling method thereof. The pixel circuit includes: a pixel display unit consisted of n sub-pixel display units, n≥3; and a data signal control unit coupled to the pixel display unit, n data lines for driving the pixel display unit and a control line. The data signal control unit is configured to, under a condition that a first control signal is input through the control line, couple the n sub-pixel display units to the n data lines for driving the n sub-pixel display units respectively; and when a second control signal is input through the control line couple one of the n data lines for driving the pixel display unit to at least one of the n sub-pixel display units in the pixel display unit.

Claims

1. A pixel circuit, comprising:

a pixel display unit, comprising n sub-pixel display units, wherein n≥

3; and

a data signal control unit, coupled to the pixel display unit, n data lines, and a control line, wherein the n data lines drive the pixel display unit,

wherein the data signal control unit is configured to, under a condition that a first control signal is input through the control line, couple the n sub-pixel display units to the n data lines configured to drive the n sub-pixel display units respectively; and

under a condition that a second control signal is input through the control line, couple one of the n data lines configured to drive the pixel display unit to at least one of the n sub-pixel display units in the pixel display unit,

wherein the first control signal is one of a high level signal and a low level signal, and the second control signal is the other one of the high level signal and the low level signal.

2. The pixel circuit according to claim 1, wherein the data signal control unit comprises n first switches, each coupled to one of the n sub-pixel display units and one of data lines, the n first switches are further coupled to the control line, and each of the n first switches is configured to switch on to couple the sub-pixel display unit to the data line under a condition that the first control signal is input through the control line, and to switch off under a condition that the second control signal is input through the control line, wherein the sub-pixel display is coupled to the first switch.

3. The pixel circuit according to claim 2, wherein the first switch is a first transistor, and the first transistor comprises a gate coupled to the control line, a first electrode coupled to the sub-pixel display unit, and a second electrode coupled to the data line.

4. The pixel circuit according to claim 1, wherein the data signal control unit comprises a second switch coupled to one of the sub-pixel display units of the pixel display unit and one of the data lines, wherein the data lines are configured to drive the pixel display unit, and the second switch is further coupled to the control line,

wherein the second switch is configured to switch on to couple the sub-pixel display unit to the data line under a condition that the second control signal is input through the control line, and to switch off under a condition that the first control signal is input through the control line, wherein the sub-pixel display unit is coupled to the second switch.

5. The pixel circuit according to claim 4, wherein the second switch is a second transistor, and the second transistor comprises a gate coupled to the control line, a first electrode coupled to the one of the sub-pixel display units of the pixel display unit, and a second electrode coupled to the one of the data lines, wherein the data lines are configured to drive the pixel display unit.

6. The pixel circuit according to claim 5, wherein, when the data signal control unit comprises the first transistors and the second transistor, the first transistor is one of an N-type transistor and a P-type transistor;

the second transistor is the other one of the N-type transistor and the P-type transistor.

7. The pixel circuit according to claim 2, wherein the data signal control unit comprises n third switches coupled to one of the data lines, wherein the data lines are configured to drive the pixel display unit,

wherein each of the n third switches is coupled to one of the sub-pixel display units of the pixel display unit and the control line, and each of the n third switches is configured to switch on to couple the data line to the sub-pixel display unit under a condition that the second control signal is input through the control line, and switch off under a condition that the first control signal is input through the control line, wherein the data line is coupled to the third switch.

8. The pixel circuit according to claim 7, wherein the third switch is a third transistor, and the third transistor comprises a gate coupled to the control line, a first electrode coupled to the one of the sub-pixel display units of the pixel display unit and a second electrode coupled to the one of the data lines, wherein the data lines are configured to drive the pixel display unit.

9. The pixel circuit according to claim 8, wherein, when the data signal control unit comprises the first transistors and the third transistors, the first transistor is one of an N-type transistor and a P-type transistor and the third transistor is the other one of the N-type transistor and the P-type transistor.

10. An array substrate, comprising a plurality of data lines and a plurality of gate lines and a plurality of sub-pixel regions that are defined by the plurality of data lines and the plurality of gate lines which cross each other in an insulated manner,

wherein one pixel region is consisted of n sub-pixel regions, and the array substrate further comprises a plurality of control lines crossing the plurality of data lines, each of pixel regions is disposed with a pixel circuit and each row of the pixel regions arranged along a direction of the gate line is coupled to one of the control lines,

wherein the pixel circuit comprises:

a pixel display unit, comprising n sub-pixel display units, wherein n≥

3; and

a data signal control unit, coupled to the pixel display unit, n data lines, and a control line, wherein the n data lines drive the pixel display unit,

wherein the data signal control unit is configured to, under a condition that a first control signal is input through the control line, couple the n sub-pixel display units to the n data lines that drive the n sub-pixel display units respectively; and

under a condition that a second control signal is input through the control line, couple one of the n data lines configured to drive the pixel display unit to at least one of the n sub-pixel display units in the pixel display unit,

wherein the first control signal is one of a high level signal and a low level signal, and the second control signal is the other one of the high level signal and the low level signal.

15. The array substrate according to claim 10, wherein the data signal control unit comprises n first switches, each coupled to one of the n sub-pixel display units and one of the data lines, the n first switches are further coupled with the control line, and each of the n first switches is configured to switch on to couple the sub-pixel display unit to the data line when the first control signal is input through the control line, and to switch off when the second control signal is input through the control line, wherein the sub-pixel display is coupled to the first switch.

16. The array substrate according to claim 15, wherein the first switch is a first transistor, and the first transistor comprises a gate coupled with the control line, a first electrode coupled with the sub-pixel display unit, and a second electrode coupled with the data line.

17. The array substrate according to claim 15, wherein the data signal control unit comprises a second switch coupled to one of the sub-pixel display units of the pixel display unit and one of the data lines, wherein the data lines are configured to drive the pixel display unit, and the second switch is further coupled to the control line,

wherein the second switch is configured to switch on to couple the sub-pixel display unit to the data line under a condition that the second control signal is input through the control line, and to switch off under a condition that the first control signal is input through the control line, wherein the sub-pixel display unit is coupled to the second switch.

18. The array substrate according to claim 17, wherein the second switch is a second transistor, and the second transistor comprises a gate coupled to the control line, a first electrode coupled to the one of the sub-pixel display units of the pixel display unit and a second electrode coupled to the one of the data lines, wherein the data lines are configured to drive the pixel display unit.

19. The array substrate according to claim 15, wherein the data signal control unit comprises n third switches coupled to one of the data lines, wherein the data lines are configured to drive the pixel display unit,

wherein each of the n third switches is coupled to one of the sub-pixel display units of the pixel display unit and the control line, and each of the n third switches is configured to switch on to couple the data line to the sub-pixel display unit under a condition that the second control signal is input through the control line, and switch off under a condition that the first control signal is input through the control line, wherein the data line is coupled to the third switch.

20. The array substrate according to claim 19, wherein the third switch is a third transistor, and the third transistor comprises a gate coupled to the control line, a first electrode coupled to the one of the sub-pixel display units of the pixel display unit and a second electrode coupled to the one of the data lines, wherein the data lines are configured to drive the pixel display unit.

12. A display device, comprising an array substrate,

wherein the array substrate comprises a plurality of data lines and a plurality of gate lines and a plurality of sub-pixel regions that are defined by the plurality of data lines and the plurality of gate lines which cross each other in an insulated manner,

wherein one pixel region is consisted of n sub-pixel regions, and the array substrate further comprises a plurality of control lines crossing the plurality of data lines, each of pixel regions is disposed with a pixel circuit and each row of the pixel regions arranged along a direction of the gate line is coupled to one of the control lines,

wherein the pixel circuit comprises:

a pixel display unit consisted of n sub-pixel display units, n≥

3; and

a data signal control unit coupled to the pixel display unit, n data lines configured to drive the pixel display unit and the control line,

wherein the data signal control unit is configured to, under a condition that a first control signal is input through the control line, couple the n sub-pixel display units to the n data lines that drive the n sub-pixel display units respectively; and

under a condition that a second control signal is input through the control line, couple one of the n data lines configured to drive the pixel display unit to at least one of the n sub-pixel display units in the pixel display unit,

wherein the first control signal is one of a high level signal and a low level signal, and the second control signal is the other one of the high level signal and the low level signal.

11. The array substrate according to claim 13, wherein the pixel display unit comprises a first sub-pixel display unit, a second sub-pixel display unit and a third sub-pixel display unit;

and

the second switches within three adjacent pixel regions along the direction of the gate line are coupled to different sub-pixel display units.

13. A method for controlling the display device according to claim 14, comprising

acquiring a viewpoint position on the display device;

and

inputting a first control signal to a first control line, such that n sub-pixel display units at the viewpoint position are coupled to n data lines configured to drive the n sub-pixel display units respectively, wherein the first control line is a control line that is coupled to a pixel circuit at the viewpoint position; and

inputting a second control signal to a second control line, such that one of the n data lines configured to drive the pixel display unit is coupled to at least one of sub-pixel display units of the pixel display unit, wherein the second control line is a control line other than the first control line,

wherein the first control signal is one of a high level signal and a low level signal, and the second control signal is the other one of the high level signal and the low level signal.

14. The display device according to claim 12, further comprising a viewpoint tracking circuit and a control circuit,

the viewpoint tracking circuit is configured to acquire a viewpoint position on the display device;

and

the control circuit is configured to input the first control signal to a first control line, such that n sub-pixel display units at the viewpoint position are coupled to n data lines configured to drive the n sub-pixel display units respectively, wherein the first control line is a control line that is coupled to a pixel circuit at the viewpoint position; and

to input the second control signal to a second control line, such that one of n data lines configured to drive the pixel display unit is coupled to at least one of the sub-pixel display units of the pixel display unit, wherein the second control line is a control line other than the first control line.