ARRAY SUBSTRATE AND MOBILE TERMINAL

• US 20190005915A1
• Filed: 06/27/2018
• Published: 01/03/2019
• Est. Priority Date: 06/28/2017
• Status: Abandoned Application

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Inventors: LIU, Ying, Liu, Anyu, Liu, Weiguang
• Application Number:
  US16/020,322
• Publication Number:
  US 20190005915A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/56 Substrates having a particular shape, e.g. non-rectangular
• CPC Class Codes: G09G 2300/02 Composition of display devices
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092

Abstract

The present disclosure relates to an array substrate and a mobile terminal. The array substrate includes a base; a notch at an edge of the base; a plurality of pixel units on the base that are configured to form a display area, wherein the display area includes a first display area including a firs set of pixel units within a first sub-edge, and a second display area including a second set of pixel units within a second sub-edge, and wherein the first sub-edge delimits a region of the edge at a first side of the notch, and the second sub-edge delimits a region of the edge at a second side of the notch; a plurality of first gate lines, each of which is shared by pixel units in a same row in the first display area; a plurality of second gate lines, each of which is shared by pixel units in a same row in the second display area; a first gate drive circuit at the first side of the notch and connected electrically with the plurality of first gate lines for driving pixel units in the first display area through respective ones of the plurality of first gate lines; and a second gate drive circuit at the second side of the notch and connected electrically with the plurality of second gate lines for driving pixel units in the second display area through respective ones of the plurality of second gate lines.

Claims

1. An array substrate, comprising:

a base;

a notch at an edge of the base;

a plurality of pixel units on the base that are configured to form a display area, wherein the display area includes a first display area including a firs set of pixel units within a first sub-edge, and a second display area including a second set of pixel units within a second sub-edge, and wherein the first sub-edge delimits a region of the edge at a first side of the notch, and the second sub-edge delimits a region of the edge at a second side of the notch;

a plurality of first gate lines, each of which is shared by pixel units in a same row in the first display area;

a plurality of second gate lines, each of which is shared by pixel units in a same row in the second display area;

a first gate drive circuit at the first side of the notch and connected electrically with the plurality of first gate lines for driving pixel units in the first display area through respective ones of the plurality of first gate lines; and

a second gate drive circuit at the second side of the notch and connected electrically with the plurality of second gate lines for driving pixel units in the second display area through respective ones of the plurality of second gate lines.

2. The array substrate according to claim 1, wherein the array substrate further comprises:

a third display area including a third set of display units that are below a bottom portion of the notch; and

a plurality of third gate lines, each of which is shared by pixel units in a same row in the third display area,

wherein the first gate drive circuit is connected electrically with the plurality of third gate lines for driving pixel units in the third display area.

3. The array substrate according to claim 2, wherein the first gate drive circuit includes a first drive unit and a second drive unit,

wherein the first drive unit is connected electrically with the plurality of first gate lines for driving pixel units in the first display area, and

wherein the second drive unit is connected electrically with the plurality of third gate lines for driving pixel units in the third display area.

4. The array substrate according to claim 1, further comprising a first non-display area having a first chive unit,

wherein the first non-display area is within a region between the notch and the first display area.

5. The array substrate according to claim 1, farther comprising a second non-display area having a second gate drive circuit,

wherein the second non-display area is within a region between the notch and the second display area.

6. The array substrate according to claim 4, further comprising at least two clock signal lines on at least one side of the display area.

7. The array substrate according to claim 5, further comprising at least two clock signal lines on at least one side of the display area.

8. The array substrate according to claim 6, wherein the at least two clock signal lines extend into the first non-display area.

9. The array substrate according to claim 6, wherein the at least two clock signal lines extend into the second non-display area.

10. The array substrate according to claim 6, wherein the at least two clock signal lines extend simultaneously into the first non-display area and the second non-display area.

11. The array substrate according to claim 7, wherein the at least two clock signal lines extend into the first non-display area.

12. The array substrate according to claim 7, wherein the at least two clock signal lines extend into the second non-display area.

13. The array substrate according to claim 7, wherein the at least two clock signal lines extend simultaneously into the first non-display area and the second non-display area.

14. The array substrate according to claim 1, further comprising a third non-display area having a first drive unit,

wherein the third non-display area is within a region between the second display area and the base.

15. The array substrate according to claim 1, further comprising a fourth non-display area having a second drive unit,

wherein the fourth non-display area is within a region between the second display area and the base.

16. A mobile terminal, comprising:

an array substrate including;

a base;

a notch at an edge of the base;

a plurality of pixel units on the base that are configured to form a display area, wherein the display area includes a first display area including a firs set of pixel units within a first sub-edge, and a second display area including a second set of pixel units within a second sub-edge, and wherein the first sub-edge delimits a region of the edge at a first side of the notch, and the second sub-edge delimits a region of the edge at a second side of the notch;

a plurality of first gate lines, each of which is shared by pixel units in a same row in the first display area;

a plurality of second gate lines, each of which is shared by pixel units in a same row in the second display area;

a first gate drive circuit at the first side of the notch and connected electrically with the plurality of first gate lines for driving pixel units in the first display area through respective ones of the plurality of first gate lines; and

a second gate drive circuit at the second side of the notch and connected electrically with the plurality of second gate lines for driving pixel units in the second display area through respective ones of the plurality of second gate lines; and

preset components provided in the notch.

17. The mobile terminal according to claim 16, wherein the preset components comprise at least one of a camera, a receiver, a speaker and a light sensor.