GLOBAL BIT LINE PRE-CHARGING AND DATA LATCHING IN MULTI-BANKED MEMORIES USING A DELAYED RESET LATCH
First Claim
1. A memory, comprising:
- a plurality of banks, wherein each bank of the plurality of banks includes a plurality of data storage cells, wherein a particular bank of the plurality of banks is configured to discharge a particular global bit line of a plurality of global bit lines in response to a memory operation;
control circuitry configured to;
receive information indicative of a control signal; and
select a first bank of the plurality of banks based upon the control signal; and
generate a plurality of bank enable signals using the control signal; and
a first latch circuit coupled to the first bank via a first global bit line of the plurality of global bit lines, and a second bank via a second global bit line of the plurality of global bit lines, wherein the first latch circuit is configured to;
store data based on a voltage level of the first global bit line;
pre-charge the first global bit line based upon the control signal;
generate a plurality of pre-charge signals using the plurality of bank enable signals; and
generate a reset signal based upon at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal.
1 Assignment
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Accused Products
Abstract
A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.
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Citations
20 Claims
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1. A memory, comprising:
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a plurality of banks, wherein each bank of the plurality of banks includes a plurality of data storage cells, wherein a particular bank of the plurality of banks is configured to discharge a particular global bit line of a plurality of global bit lines in response to a memory operation; control circuitry configured to; receive information indicative of a control signal; and select a first bank of the plurality of banks based upon the control signal; and generate a plurality of bank enable signals using the control signal; and a first latch circuit coupled to the first bank via a first global bit line of the plurality of global bit lines, and a second bank via a second global bit line of the plurality of global bit lines, wherein the first latch circuit is configured to; store data based on a voltage level of the first global bit line; pre-charge the first global bit line based upon the control signal; generate a plurality of pre-charge signals using the plurality of bank enable signals; and generate a reset signal based upon at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal. - View Dependent Claims (2, 4, 6)
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3. (canceled)
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5. (canceled)
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7. A method, comprising:
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receiving, by a multi-bank memory, data indicative of an address location in the multi-bank memory; decoding the data indicative of the address location to generate a decoded address; generating a plurality of pre-charge signals using the decoded address; initiating a read operation of a particular bank of a plurality of banks included in the multi-bank memory using the decoded address, wherein initiating the read operation includes; pre-charging, using the plurality of pre-charge signals, a particular global bit line of a plurality of global bit lines coupled to the particular bank; generating a reset signal using at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal; storing, in a first latch circuit, data based on a voltage level of the particular global bit line using the plurality of pre-charge signals; and resetting the first latch circuit using the reset signal. - View Dependent Claims (9, 10, 12, 13)
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8. (canceled)
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11. (canceled)
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14. A system, comprising:
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a processor; and a memory coupled to the processor, wherein the memory includes a plurality of banks, wherein each bank of the plurality of banks includes a plurality of data storage cells, and wherein the memory is configured to; receive an access operation from the processor; decode an address included in the access operation to generated a decoded address; select a particular bank of the plurality of banks using the decoded address; generate a plurality of pre-charge signals using a plurality of bank enable signals that are based upon the decoded address; store a data value based upon a voltage level of a global bit line coupled to the particular bank using the plurality of pre-charge signals; and pre-charge the global bit line using a particular pre-charge signal of the plurality of pre-charge signals. - View Dependent Claims (15, 16, 17, 18, 20)
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19. (canceled)
Specification