MEMORY DEVICE CAPABLE OF SUPPORTING MULTIPLE READ OPERATIONS

• US 20190006012A1
• Filed: 05/25/2018
• Published: 01/03/2019
• Est. Priority Date: 06/29/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SHIN, Kye-Wan
• Granted Patent: US 10,497,447 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.

Claims

1. A memory device comprising:

at least one first memory cell of first plane;

at least one second memory cell of second plane; and

a control circuit suitable for performing multiple read operations on the at least one first memory cell and the at least one second memory cell in response to a read command,

wherein the multiple read operations comprise a first read operation, which is performed on the at least one first memory cell in a first read period, and a second read operation which is performed on the at least second memory cell in a second read period.

2. The memory device of claim 1, wherein the first and second planes comprise different numbers of memory blocks.

3. The memory device of claim 1, wherein the first and second planes comprise single level cells (SLCs).

4. The memory device of claim 1, further comprising a voltage generation circuit suitable for generating an operation voltage, a read voltage and a pass voltage for the first and second read operations.

5. The memory device of claim 4, wherein the control circuit controls the voltage generation circuit to apply the operation voltage to a drain select line, to apply the read voltage to a word line selected for a read operation, and to apply the pass voltage to an unselected word line, and precharges a selected bit line.

6. The memory device of claim 5, wherein each of the first and second read periods comprises a first period in which the operation voltage is applied to the drain select line, a second period in which the read voltage is applied to the selected word line and the pass voltage is applied to the unselected word line, and a third period in which the selected bit line is precharged.

7. The memory device of claim 6, wherein the first and second periods have the same start timing.

8. The memory device of claim 6, wherein the first and second periods have different start timings.

9. The memory device of claim 6, wherein the second and third periods have the same start timing.

10. The memory device of claim 6, wherein the second and third periods have different start timings.

11. A memory device comprising:

a plurality of memory planes; and

a control circuit suitable for controlling plural read operations to be performed on different memory planes in different speeds in response to a read command.

12. The memory device of claim 11, wherein the plurality of planes comprises different numbers of memory blocks, respectively.

13. The memory device of claim 11, wherein each of the memory planes comprises single level cells (SLCs).

14. The memory device of claim 11, further comprising a voltage generation circuit suitable for generating an operation voltage, a read voltage and a pass voltage for the plural read operations.

15. The memory device of claim 14, wherein the control circuit controls the voltage generation circuit to apply the operation voltage to a drain select line, to apply the read voltage to a word line selected for the plural read operations, and to apply the pass voltage to an unselected word line, and precharges a selected bit line.

16. The memory device of claim 15, wherein the read operation comprises a first operation of applying the operation voltage to the drain select line, a second operation of applying the read voltage to the selected word line and applying the pass voltage to the unselected word line, and a third operation of precharging the selected bit line.

17. The memory device of claim 16, wherein the first and second operations have the same start timing.

18. The memory device of claim 16, wherein the first and second operations have different start timings.

19. The memory device of claim 16, wherein the second and third operations have the same start timing.

20. The memory device of claim 16, wherein the second and third operations have different start timings.

21. A memory device comprising:

a plurality of memory planes, each having different number of memory blocks; and

a control circuit suitable for controlling plural read operations to be performed on different memory planes in different speeds, depending on the number of memory block, in response to a read command.