Semiconductor Package with Cavity

• US 20190006252A1
• Filed: 06/30/2017
• Published: 01/03/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Akkinepally, Praneeth
• Granted Patent: US 10,410,940 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/10 the devices having separate containers
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.

Claims

1. A semiconductor package comprising:

a first die including first and second sidewalls;

a first cavity including first and second sidewalls each comprising a first dielectric material;

a second dielectric material directly contacting the first and second sidewalls of the first die;

a first layer, on the first die, which includes a first metal interconnect and a third dielectric material;

wherein (a) a first horizontal axis intersects the first and second sidewalls of the first die, the first and second sidewalls of the first cavity, and the second dielectric material, but does not intersect the first layer, and (b) a second horizontal axis intersects the first metal interconnect the third dielectric material.

2. The package of claim 1 wherein the first dielectric material directly contacts the second dielectric material along a seam and the first horizontal axis intersects the first seam.

3. The package of claim 2 wherein the first and second dielectric materials include different material compositions from each other.

4. The package of claim 2 wherein the first and second dielectric materials have substantially equal material compositions to one another.

5. The package of claim 2 wherein the first metal interconnect includes a via that is completely filled with at least one metal.

6. The package of claim 5 comprising at least one solder ball, wherein the first layer is between the at least one solder ball and the first die.

7. The package of claim 5 wherein a first vertical axis intersects the first layer and the first die.

8. The package of claim 7 wherein the first and second sidewalls of the first cavity are substantially parallel to the first vertical axis.

9. The package of claim 7 wherein the first and second sidewalls of the first cavity are:

(a) not parallel to the first vertical axis, (b) not parallel to the first horizontal axis, and (c) tapered.

10. The package of claim 7 wherein the first vertical axis intersects the second dielectric material.

11. The package of claim 10 wherein the second dielectric material directly contacts the first die at a location between the first die and the first layer.

12. The package of claim 2 wherein the second dielectric material directly contacts the first die at a location between the first die and the first layer.

13. The package of claim 2 wherein the first and second dielectric materials are not monolithic with each other.

14. The package of claim 2 comprising a second die, wherein the first horizontal axis intersects the first and second dies.

15. The package of claim 14 comprising:

a second cavity including first and second sidewalls each comprising the first dielectric material;

the second dielectric material directly contacting the first and second sidewalls of the second die; and

the first layer on the second die;

wherein the first horizontal axis intersects the first and second sidewalls of the second die, and the first and second sidewalls of the second cavity.

16. The package of claim 2 wherein the package does not include a through silicon via (TSV).

17. A semiconductor package system comprising:

a first package including;

(a)(i) a first die including first and second sidewalls, (a)(ii) a first cavity including first and second sidewalls each comprising a first dielectric material;

(a)(iii) a second dielectric material directly contacting the first and second sidewalls of the first die;

(a)(iv) a first layer, on the first die, which includes a first metal interconnect and a third dielectric material; and

a second package including a second die;

wherein (b)(i) a first horizontal axis intersects the first and second sidewalls of the first die, the first and second sidewalls of the first cavity, and the second dielectric material, but does not intersect the first layer and does not intersect the second die, (b)(ii) a second horizontal axis intersects the first metal interconnect the third dielectric material, and (b)(iii) a vertical axis intersects the first and second dies.

18. The system of claim 17 comprising at least one solder ball that couples the first die to the second die.

19. The system of claim 17 comprising:

a void between first and second dies and having a lower boundary defined at least in part by an upper surface of the first package and an opposing second boundary defined at least in part by a lower surface of the second package;

wherein (c)(i) a portion of the upper surface of the first package directly over the first die is a first distance away from the first layer, (c)(ii) a second portion of the upper surface of the first package that is not directly over the first die is a second distance away from the first layer, and (c)(iii) the first distance is greater than the second distance.

20. The system of claim 19 wherein:

the vertical axis intersects the first portion of the upper surface of the first package; and

the vertical axis does not intersect the second portion of the upper surface of the first package.

21. The system of claim 17 wherein the first die includes a processor and the second die includes a memory.

22. A method comprising:

coupling a sacrificial material to a substrate;

forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material;

forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material;

decoupling the substrate from the first dielectric material and the sacrificial material;

removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material;

after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and

forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die.

23. The method of claim 22 comprising forming an interconnect through the first dielectric material, wherein a first vertical axis intersects the interconnect but does not intersect the first die after the first die is inserted into the empty cavity.

24. The method of claim 23 comprising forming the interconnect through the first dielectric before decoupling the substrate from the first dielectric material and the sacrificial material.

25. The method of claim 23 comprising forming the interconnect through the first dielectric after decoupling the substrate from the first dielectric material and the sacrificial material.