BACKPLANE LED INTEGRATION AND FUNCTIONALIZATION STRUCTURES

• US 20190006329A1
• Filed: 01/11/2017
• Published: 01/03/2019
• Est. Priority Date: 01/12/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hashim, Imran, Patel, Vaibhav D., Hu, Hsin-Hua, Sakariya, Kapil V., Kauffman, Ralph E.
• Granted Patent: US 10,497,682 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall passivation layer is formed around the LEDs. The sidewall passivation layer may or may not be contained within a well structure. A top electrode layer is formed to electrically connect the LEDs to conductive terminal routing.

Claims

1. A display comprising:

an array of pads, and a corresponding array of light emitting diodes (LEDs) bonded to the array of pads;

an array of conductive terminal well structures, each conductive terminal well structure including conductive terminal sidewalls that surround at least one LED;

a sidewall passivation layer around each of the LEDs in the array of LEDs and contained within the conductive terminal well structures; and

an electrode layer on and in electrical contact with the array of LEDs and the array of conductive terminal sidewalls.

2. The display of claim 1, further comprising a passivation layer including a first array of openings over the array of pads and a second array of openings over an array of conductive terminal pads.

3. The display of claim 2, wherein the conductive terminal sidewalls connect adjacent conductive terminal pads and span over the passivation layer.

4. The display of claim 3, further comprising a conductive terminal sidewall adhesion layer on the conductive terminal sidewalls and an array of pad adhesion layers on the array of pads, wherein the array of pad adhesion layers are electrically insulated from the conductive terminal sidewall adhesion layer.

5. The display of claim 4, wherein the sidewall passivation layer is in direct contact with the conductive terminal sidewall adhesion layer on the conductive terminal sidewalls.

6. The display of claim 4, wherein the conductive terminal sidewall adhesion layer and the array of pad adhesion layers comprise tantalum nitride.

7. The display of claim 1, wherein conductive terminal sidewalls are shared between adjacent conductive terminal wells.

8. The display of claim 1, wherein each conductive terminal well structure includes conductive terminal sidewalls surrounding a single subpixel.

9. The display of claim 8, wherein each subpixel includes a pair of independently addressable pads, and a corresponding pair of LEDs.

10. The display of claim 1, wherein the sidewall passivation layer includes a level top surface within the array of conductive terminal well structures.

11. A display comprising:

an array of pads, and a corresponding array of LEDs bonded to the array of pads;

an array of conductive terminal pads, and a corresponding array of conductive terminal studs on the conductive terminal pads;

a sidewall passivation layer around each of the LEDs in the array of LEDs; and

an electrode layer on and in electrical contact with the array of LEDs and the array of conductive terminal studs.

12. The display of claim 11, wherein the sidewall passivation layer includes a level top surface around the array of LEDs.

13. The display of claim 11, further comprising a bank layer including an array of bank openings over the array of pads, and an array of terminal stud openings over the array of conductive terminal studs;

wherein the electrode layer is formed over the bank layer, and the sidewall passivation layer is contained within the array of bank openings.

14. The display of claim 13, wherein sidewalls of each bank opening surround one corresponding subpixel.

15. The display of claim 11, wherein the sidewall passivation layer surrounds each of the conductive terminal studs in the array of conductive terminal studs.

16. The display of claim 15:

further comprising a conductive terminal adhesion layer on the array of conductive terminal studs and an array of pad adhesion layers on the array of pads;

wherein the sidewall passivation layer is in direct contact with the conductive terminal adhesion layer on the array of conductive terminal studs.

17. The display of claim 11 further comprising:

an array of conductive terminal lines connecting the array of conductive terminal pads; and

a conductive terminal adhesion layer on the array of conductive terminal studs and the array of conductive terminal lines connecting the array of conductive terminal pads;

wherein the sidewall passivation layer is formed over the conductive terminal adhesion layer that is formed on the array of conductive terminal lines.

18. A display comprising:

an array of pads, and a corresponding array of LEDs bonded to the array of pads;

an array of conductive terminal pads;

a sidewall passivation layer around each of the LEDs in the array of LEDs;

an array of openings in the sidewall passivation layer over the array of conductive terminal pads; and

an electrode layer on and in electrical contact with the array of LEDs and the array of conductive terminal pads.

19. The display of claim 18, further comprising an array of conductive terminal lines connecting the array of conductive terminal pads, and the sidewall passivation layer is formed over the array of conductive terminal lines.

20. The display of claim 19, further comprising a conductive terminal adhesion layer on the array of conductive terminal pads and the array of conductive terminal lines.

21. The display of claim 19, wherein each conductive terminal pad overlaps across two adjacent pixel areas.

22. The display of claim 18, wherein the sidewall passivation layer includes a level top surface around the array of LEDs.