SOLID-STATE IMAGE SENSING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS

• US 20190006410A1
• Filed: 06/24/2016
• Published: 01/03/2019
• Est. Priority Date: 07/10/2015
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: TAKAHASHI, SHINGO
• Granted Patent: US 10,453,887 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 14/025 Metallic sublayers
• CPC Class Codes: C23C 14/165 by cathodic sputtering
• CPC Class Codes: C23C 14/345 using substrate bias
• CPC Class Codes: C23C 14/3492 Variation of parameters during sputtering
• CPC Class Codes: C23C 14/541 Heating or cooling of the substrates
• CPC Class Codes: H01L 21/285 from a gas or vapour, e.g. condensation
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/3205 Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/14 : including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/146 : Imager structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/14641 : Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H04N 25/40 : Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/67 : applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/70 : SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/745 : Circuitry for generating timing or clock signals

Abstract

The present disclosure relates to a solid-state image sensing device, a manufacturing method, and an electronic apparatus, in which surface roughness on a wiring surface can be suppressed. In redistribution layer forming processing, a Ti/Cu film corresponds to a barrier layer and a seed layer is formed by Ti/Cu sputtering after opening a through-silicon via. At this point, actually, degassing heating, reverse sputtering, Ti deposition, and Seed-Cu deposition are sequentially performed. As a method of depositing a Seed-Cu film having high crystallinity in deposition of the Seed-Cu film, performing deposition by increasing a substrate temperature to a high temperature is one method, and the Seed-Cu film of Cu(111)/(200) is formed by performing deposition at the substrate temperature of 60 degrees or more, and Cu haze are suppressed. The present disclosure can be applied to, for example, a CMOS solid-state image sensing device used as an imaging device such as a camera.

Claims

1. A solid-state image sensing device comprising a barrier layer and a plated power supply layer as a redistribution layer,

wherein crystallinity of a film of the plated power supply layer is controlled at the time of depositing a film of the barrier layer and the film of the plated power supply layer.

2. The solid-state image sensing device according to claim 1, wherein

the film of the barrier layer is a Ti film, and

the film of the plated power supply layer is a Cu film.

3. The solid-state image sensing device according to claim 2, wherein the Cu film is highly oriented to Cu(111).

4. The solid-state image sensing device according to claim 2, wherein the Cu film has crystallinity with a strength ratio of Cu(111)/Cu(200)≥

200.

5. The solid-state image sensing device according to claim 2, wherein the Cu film is deposited at a substrate temperature of 60 degrees or more.

6. The solid-state image sensing device according to claim 5, wherein the substrate temperature is increased by heating the substrate temperature to 60 degrees or more.

7. The solid-state image sensing device according to claim 5, wherein the substrate temperature is increased by setting target power to high power.

8. The solid-state image sensing device according to claim 5, wherein the substrate temperature is increased by applying bias to the substrate to cause sputter ions entering the substrate to have high energy.

9. The solid-state image sensing device according to claim 2, wherein

the Ti film is highly oriented to Ti(002), and

the Cu film is deposited on the Ti film.

10. A manufacturing method to control crystallinity of a film of a plated power supply layer when a manufacturing device of a solid-state image sensing device deposits a film of a barrier layer and the film of the plated power supply layer in a course of forming a redistribution layer.

11. An electronic apparatus comprising a barrier layer and a plated power supply layer as redistribution layers,

wherein provided are:

a solid-state image sensing device in which crystallinity of a film of the plated power supply layer is controlled at the time of depositing a film of the barrier layer and the film of the plated power supply layer;

a signal processing circuit configured to process an output signal output from the solid-state image sensing device; and

an optical system configured to allow incident light to enter the solid-state image sensing device.