RANDOM NUMBER GENERATOR

• US 20190012148A1
• Filed: 09/14/2018
• Published: 01/10/2019
• Est. Priority Date: 07/02/2014
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: HADDAD, Patrick, FISCHER, Viktor
• Granted Patent: US 10,445,068 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.

Claims

1. A random number generation circuit, comprising:

a first logic gate;

a second logic gate;

a first adjustable delay element assembly coupled in series between an output of the first logic gate and an input of the second logic gate;

a second adjustable delay element assembly coupled in series between an output of the second logic gate and an input of the first logic gate; and

a digitizing circuit coupled to an output of the second adjustable delay element, wherein the digitizing circuit comprises;

an asynchronous counter, wherein an input of the asynchronous counter is coupled to the output of the second adjustable delay element; and

a sampling circuit to sample an output of the asynchronous counter.

2. The random number generation circuit of claim 1, wherein the asynchronous counter comprises:

a number of D-type flip-flops equal to a corresponding to number of random state bits provided per generation period.

3. The random number generation circuit of claim 1, wherein the sampling circuit includes an input node configured to receive a control signal, the sampling circuit being configured to generate a random number in response to being triggered by the control signal.

4. The random number generation circuit of claim 1, wherein each adjustable delay element assembly comprises:

a first sub-assembly configured to provide a fixed delay; and

a second sub-assembly configured to provide a selectable delay.

5. The random number generation circuit of claim 4, wherein the second sub-assembly comprises:

at least two delay element circuits, a first one of the delay element circuits having a first number of delay elements connected in series, and a second one of the delay element circuits having a second number of delay elements connected in series, the first number being different from the second number.

6. The random number generation circuit of claim 4, wherein the at least two delay element circuits are coupled in parallel to each other.

7. The random number generation circuit of claim 6, wherein the second sub-assembly comprises:

a multiplexer, each of the at least two delay element circuits providing an input to the multiplexer, an output of the multiplexer providing an output of the second sub-assembly.

8. The random number generation circuit of claim 4, wherein each second sub-assembly comprises:

a plurality of series-connected delay elements, each one of the plurality of series-connected delay elements coupled in parallel with the other ones of the plurality of series-connected delay elements, the adjustable delay provided by selecting one of the groups plurality of series-connected delay elements, wherein each one of the plurality of series-connected delay elements includes at least two delay elements coupled in series.

9. The random number generation circuit of claim 1, comprising:

a first multiplexer interposed between an output of the first random number delay element assembly and a first input of the second logic gate; and

a second multiplexer interposed between an output of the second adjustable delay element and a first input of the first logic gate.

10. The random number generation circuit of claim 1, wherein respective second inputs of the first and second logic gates are configured to receive a control signal, the control signal being configured to initiate generation of a random signal.

11. A method of generating a random number, comprising:

passing a first signal from a first logic gate into a first adjustable delay element assembly;

passing a second signal from the first adjustable delay element assembly into a second logic gate;

passing a third signal from the second logic gate into a second adjustable delay element assembly;

passing a fourth signal from the second adjustable delay element assembly into the first logic gate;

passing the fourth signal into a digitizing circuit; and

producing the random number with the digitizing circuit, wherein producing the random number with the digitizing circuit comprises;

passing the fourth signal into an asynchronous counter; and

sampling an output of the asynchronous counter.

12. The method of generating the random number of claim 11, comprising:

producing the second signal from the first signal by delaying the first signal, the first signal delayed with a first sub-assembly circuit that provides a non-adjustable delay and the first signal further delayed with a second sub-assembly that provides an adjustable delay.

13. The method of generating the random number of claim 12, wherein producing the second signal from the first signal comprises:

passing the further delayed first signal through one of a plurality of groups of series-connected delay elements, each one of the groups of series-connected delay elements having a different number of delay elements coupled in series.

14. The method of generating the random number of claim 13, wherein passing the further delayed first signal through one of the plurality of groups of series-connected delay elements comprises:

selecting the one of the plurality of groups of series-connected delay elements with a control signal, the control signal applied to a multiplexer.

15. The method of generating the random number of claim 11, wherein passing the fourth signal into the asynchronous counter comprises:

passing the fourth signal through a number of D-type flip-flops equal to a corresponding number of random state bits provided per generating period.

16. A system, comprising:

two logic gates;

two adjustable delay element assemblies, each of the two adjustable delay element assemblies being coupled between the two logic gates, each of the two adjustable delay element assemblies having a first sub-assembly arranged to provide a fixed delay and a second sub-assembly arranged to provide a selectable delay;

a digitizing circuit coupled to an output of one of the two adjustable delay element assemblies, the digitizing circuit having;

an asynchronous counter coupled to one of the two adjustable delay element assemblies; and

a sampling circuit to sample an output of the asynchronous counter.

17. The system of claim 16, wherein the asynchronous counter comprises:

a number of D-type flip-flops equal to a corresponding to number of random state bits provided per generation period.

18. The system of claim 16, wherein the sampling circuit includes an input node configured to receive a control signal, the sampling circuit being configured to generate a random number in response to being triggered by the control signal.

19. The system of claim 16, wherein the second sub-assembly comprises:

a multiplexer, each of the at least two delay element circuits providing an input to the multiplexer, an output of the multiplexer providing an output of the second sub-assembly.

20. The system of claim 16, comprising:

a first multiplexer interposed between an output of the second random number delay element assembly and an input of a first one of the two logic gates; and

a second multiplexer interposed between an output of the first adjustable delay element and an input of a second one of the two logic gates.