TIE-HIGH AND TIE-LOW CIRCUITS

• US 20190012419A1
• Filed: 05/21/2018
• Published: 01/10/2019
• Est. Priority Date: 07/06/2017
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated (SK Hynix Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: KONG, Wan Chul
• Granted Patent: US 10,643,013 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A tie-high circuit includes: a p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library; and a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor, wherein the decoupling capacitor comprises an n-type metal-oxide-semiconductor (NMOS) transistor having a source and a drain, either one of the source and the drain of the NMOS transistor being connected to the ground rail via an active resistor. A tie-low circuit includes: an n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in a standard cell library; and a decoupling capacitor connected to a power rail in the standard cell library and the NMOS transistor, wherein the decoupling capacitor comprises a p-type metal-oxide-semiconductor (PMOS) transistor having a source and a drain, either one of the source and the drain of the PMOS transistor being connected to the power rail via an active resistor.

Claims

1. A tie-high circuit, comprising:

a p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library; and

a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor,

wherein the decoupling capacitor comprises an n-type metal-oxide-semiconductor (NMOS) transistor having a source and a drain, either one of the source and the drain of the NMOS transistor being connected to the ground rail via an active resistor.

2. The circuit of claim 1, wherein said either one of the source and the drain of the NMOS transistor is connected to a gate of the PMOS transistor.

3. The circuit of claim 2, wherein a gate of the NMOS transistor is connected to a drain of the PMOS transistor, and an output of the tie-high circuit is provided at the drain of the PMOS transistor.

4. The circuit of claim 3, wherein a source of the PMOS transistor is connected to the power rail.

5. The circuit of claim 4, wherein in response to a supply voltage (VDD) being applied to the power rail, the supply voltage (VDD) is divided according to a ratio of an on resistance of the PMOS transistor to an effective resistance of the NMOS transistor so that the output of the tie-high circuit is provided at the drain of the PMOS transistor.

6. A tie-low circuit, comprising:

an n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in a standard cell library; and

a decoupling capacitor connected to a power rail in the standard cell library and the NMOS transistor,

wherein the decoupling capacitor comprises a p-type metal-oxide-semiconductor (PMOS) transistor having a source and a drain, either one of the source and the drain of the PMOS transistor being connected to the power rail via an active resistor.

7. The circuit of claim 6, wherein said either one of the source and the drain of the PMOS transistor is connected to a gate of the NMOS transistor.

8. The circuit of claim 7, wherein a gate of the PMOS transistor is connected to a drain of the NMOS transistor, and an output of the tie-low circuit is provided at the drain of the NMOS transistor.

9. The circuit of claim 8, wherein a source of the NMOS transistor is connected to the ground rail.

10. The circuit of claim 9, wherein in response to a supply voltage (VDD) being applied to the power rail, the supply voltage (VDD) is divided according to a ratio of an effective resistance of the PMOS transistor to an on resistance of the NMOS transistor so that the output of the tie-low circuit is provided at the drain of the NMOS transistor.