SHIFT REGISTER, GATE DRIVER, AND DRIVING METHOD OF SHIFT REGISTER
First Claim
1. A shift register comprising:
- a first capacitor with a first terminal connected to a first pull-up node and a second terminal connected to a second pull-up node;
a first thin-film transistor with a gate connected to the first pull-up node, a first electrode connected to the second pull-up node, and a second electrode connected to a first clock signal input terminal;
a second thin-film transistor with a gate connected to the second pull-up node, a first electrode connected to an output of the shift register, and a second electrode connected to a DC high level signal terminal; and
an input control circuit connected to a first signal input terminal and a first signal control terminal, configured to control a voltage level of the first terminal of the first capacitor under the control of a first input signal inputted from the first signal input terminal and a first control signal inputted from the first signal control terminal,wherein, the first capacitor and the first thin-film transistor boost the voltage on the first pull-up node so as to make a clock signal inputted from the first clock signal input terminal pass to the second pull-up node, and enable a high level signal inputted from the DC high level signal terminal to control the output of the shift register via the second thin-film transistor when the voltage level of the first terminal of the first capacitor is a turn-on voltage level.
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Accused Products
Abstract
The present disclosure discloses a shift register, comprising: a first capacitor with a first terminal connected to a first pull-up node and a second terminal connected to a second pull-up node; a first thin-film transistor with a gate connected to the first pull-up node, a first electrode connected to the second pull-up node and a second electrode connected to a first clock signal input terminal; a second thin-film transistor with a gate connected to the second pull-up node, a first electrode connected to an output of the shift register, and a second electrode connected to a DC high level signal terminal; and an input control circuit The first capacitor, the first capacitor and the first thin-film transistor boost the voltage on the first pull-up node so as to make a clock signal inputted from the first clock signal input terminal pass to the second pull-up node.
16 Citations
19 Claims
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1. A shift register comprising:
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a first capacitor with a first terminal connected to a first pull-up node and a second terminal connected to a second pull-up node; a first thin-film transistor with a gate connected to the first pull-up node, a first electrode connected to the second pull-up node, and a second electrode connected to a first clock signal input terminal; a second thin-film transistor with a gate connected to the second pull-up node, a first electrode connected to an output of the shift register, and a second electrode connected to a DC high level signal terminal; and an input control circuit connected to a first signal input terminal and a first signal control terminal, configured to control a voltage level of the first terminal of the first capacitor under the control of a first input signal inputted from the first signal input terminal and a first control signal inputted from the first signal control terminal, wherein, the first capacitor and the first thin-film transistor boost the voltage on the first pull-up node so as to make a clock signal inputted from the first clock signal input terminal pass to the second pull-up node, and enable a high level signal inputted from the DC high level signal terminal to control the output of the shift register via the second thin-film transistor when the voltage level of the first terminal of the first capacitor is a turn-on voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19)
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12. (canceled)
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13. (canceled)
Specification