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NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS EMPLOYING NVM MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS

  • US 20190019538A1
  • Filed: 11/20/2017
  • Published: 01/17/2019
  • Est. Priority Date: 07/13/2017
  • Status: Active Grant
First Claim
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1. A non-volatile (NV) memory (NVM) matrix circuit, comprising:

  • a plurality of word lines configured to receive an input vector represented by an input voltage on each word line among the plurality of word lines;

    a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;

    a plurality of source lines;

    a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of NVM bit cell circuits;

    each NVM bit cell circuit among the plurality of NVM bit cell circuits having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;

    each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit, comprising;

    a gate node coupled to a corresponding word line among the plurality of word lines; and

    each NVM bit cell circuit configured to couple its resistance to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node; and

    a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line;

    each access transistor among the plurality of access transistors comprising an access gate node coupled to an access line; and

    each access transistor among the plurality of access transistors configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in response to an access voltage applied to the access gate node.

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