NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS EMPLOYING NVM MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS

• US 20190019538A1
• Filed: 11/20/2017
• Published: 01/17/2019
• Est. Priority Date: 07/13/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Li, Xia, Yang, Bin, Tao, Gengming
• Granted Patent: US 10,482,929 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 19/18 using galvano-magnetic devices, e.g. Hall-effect devices

Abstract

Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit'"'"'s resistance to its respective source line.

Claims

1. A non-volatile (NV) memory (NVM) matrix circuit, comprising:

a plurality of word lines configured to receive an input vector represented by an input voltage on each word line among the plurality of word lines;

a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;

a plurality of source lines;

a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of NVM bit cell circuits;

each NVM bit cell circuit among the plurality of NVM bit cell circuits having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;

each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit, comprising;

a gate node coupled to a corresponding word line among the plurality of word lines; and

each NVM bit cell circuit configured to couple its resistance to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node; and

a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line;

each access transistor among the plurality of access transistors comprising an access gate node coupled to an access line; and

each access transistor among the plurality of access transistors configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in response to an access voltage applied to the access gate node.

2. The NVM matrix circuit of claim 1, wherein none of the plurality of word lines are cross-connected to any of the plurality of bit lines.

3. The NVM matrix circuit of claim 1, wherein each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit further comprises a semiconductor channel configured to be electrically coupled to the source line to couple the channel resistance of the NVM bit cell circuit to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node.

4. The NVM matrix circuit of claim 1, further comprising a plurality of second access transistors, each second access transistor among the plurality of second access transistors coupled to a corresponding source line among the plurality of source lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits;

each second access transistor among the plurality of second access transistors comprising;

a second access gate node coupled to a second access line; and

a second semiconductor channel configured to electrically couple the corresponding source line to the corresponding NVM storage string circuit in response to the input voltage applied to the second access gate node.

5. The NVM matrix circuit of claim 1, wherein an NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line among the plurality of source lines coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits.

6. The NVM matrix circuit of claim 5, wherein an amplitude of the current flowing through the source line represents a dot product multiplication of a data vector of the NVM bit cell circuit coupled to the source line, by the input vector.

7. The NVM matrix circuit of claim 1, wherein each NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits.

8. The NVM matrix circuit of claim 5, wherein amplitudes of each of the respective currents flowing through the plurality of source lines represents a dot product multiplication of data vectors of the respective NVM bit cell circuit coupled to the respective source line, by the input vector.

9. The NVM matrix circuit of claim 1, wherein one or more NVM bit cell circuits in an NVM storage string circuit among the plurality of NVM storage string circuits is configured to write a memory state based on a write activation voltage applied to the gate node of the NVM bit cell circuit.

10. The NVM matrix circuit of claim 9, wherein the one or more NVM bit cell circuits in the NVM storage string circuit among the plurality of NVM storage string circuits is further configured to write the memory state in response to a read activation voltage different from the write activation voltage and applied to the gate node of the NVM bit cell circuit in the NVM storage string circuit not being written.

11. The NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise a NAND NVM bit cell circuit comprising the plurality of NVM bit cell circuits configured to couple its resistance in series on the source line in response to the input voltage applied to its gate node.

12. The NVM matrix circuit of claim 11, wherein each NVM bit cell circuit in a respective NVM storage string circuit among the plurality of NVM storage string circuits comprises a source node coupled to a drain node of an adjacent NVM bit cell circuit.

13. The NVM matrix circuit of claim 11, wherein each NAND NVM bit cell circuit is comprised from the group consisting of a NAND NVM flash circuit and a NAND NVM Ferroelectric (Fe) Field-Effect Transistor (FET) (FeFET) circuit.

14. The NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise an AND NVM bit cell circuit comprising the plurality of NVM bit cell circuits configured to couple its resistance in parallel between its corresponding bit line and corresponding source line in response to the input voltage applied to its gate node.

15. The NVM matrix circuit of claim 14, wherein each NVM bit cell circuit in a respective NVM storage string circuit among the plurality of NVM storage string circuits comprises a source node coupled to a drain node of an adjacent NVM bit cell circuit coupled to a bit line among the plurality of bit lines, and the drain node coupled to the source line coupled to the NVM storage string circuit.

16. The NVM matrix circuit of claim 14, wherein each AND NVM bit cell circuit is comprised from the group consisting of an AND NVM flash circuit, an AND NVM FeFET circuit, an AND NVM magneto-resistive random access memory (MRAM) NVM circuit, and an AND NVM resistive random access memory (RRAM) circuit.

17. The NVM matrix circuit of claim 1, wherein the plurality of NVM storage string circuits each comprise a NOR NVM bit cell circuit comprising the plurality of NVM bit cell circuits configured to couple its resistance to the respective source line in response to the input voltage applied to its gate node.

18. The NVM matrix circuit of claim 17, wherein each NOR NVM bit cell circuit is comprised from the group consisting of a NOR NVM flash circuit, a NOR NVM FeFET circuit, a NOR NVM magneto-resistive random access memory (MRAM) circuit, and a NOR NVM resistive random access memory (RRAM) circuit.

19. The NVM matrix circuit of claim 1 integrated into an integrated circuit (IC).

20. The NVM matrix circuit of claim 1 integrated into a system-on-a-chip (SoC).

21. The NVM matrix circuit of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a global positioning system (GPS) device;

a mobile phone;

a cellular phone;

a smart phone;

a session initiation protocol (SIP) phone;

a tablet;

a phablet;

a server;

a computer;

a portable computer;

a mobile computing device;

a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.);

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player;

a portable digital video player;

an automobile;

a vehicle component;

avionics systems;

a drone; and

a multicopter.

22. A non-volatile (NV) memory (NVM) matrix circuit, comprising:

a plurality of means for applying a plurality of input voltages representing an input vector;

a plurality of means for applying a plurality of line voltages;

a plurality of means for providing a plurality of output currents representing an output vector;

a plurality of NVM storage string means each electrically coupled to a corresponding means for applying an input voltage among the plurality of means for applying the plurality of input voltages and a corresponding means for providing an output current among the plurality of means for providing the plurality of output currents, each of the plurality of NVM storage string means, comprising;

a plurality of NV means for storing a memory state each having a resistance representing the stored memory state to form a data vector for a corresponding NVM storage string means among the plurality of NVM storage string means;

each plurality of NV means for storing the memory state, comprising;

a means for electrically coupling the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents; and

a means for controlling coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents; and

a plurality of access means for controlling the means for electrically coupling the corresponding means for applying the input voltage among the plurality of means for applying the plurality of input voltages to a corresponding NVM storage string means in the coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents.

23. A method of performing matrix multiplication in a non-volatile (NV) memory (NVM) matrix circuit, comprising:

applying a line voltage on at least one bit line among a plurality of bit lines coupled to a corresponding NVM storage string circuit among a plurality of NVM storage string circuits, to electrically couple the line voltage to the corresponding NVM storage string circuit coupled to a corresponding bit line among the plurality of bit lines, each NVM storage string circuit among the plurality of NVM storage string circuits comprising a plurality of NVM bit cell circuits each having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;

applying a second line voltage on at least one source line among a plurality of source lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits, to electrically couple the second line voltage to the corresponding NVM storage string circuit coupled to a corresponding source line among the plurality of source lines;

applying a plurality of input voltages representing an input vector on a plurality of word lines, each word line among the plurality of word lines coupled to a corresponding gate node of an NVM bit cell circuit in each of the plurality of NVM storage string circuits, to electrically couple the NVM bit cell circuit to the source line to couple the resistance of the NVM bit cell circuit to the source line; and

applying an access voltage to a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line, to electrically couple the corresponding bit line to the corresponding NVM storage string circuit.

24. The method of claim 23, further comprising generating a current flowing through a respective source line among the plurality of sources lines to a respective output node coupled to a respective NVM storage string circuit among the plurality of NVM storage string circuits based on a voltage applied to the bit line coupled to the respective NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the respective NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits in the respective NVM storage string circuit.

25. The method of claim 24, wherein an amplitude of the current flowing through the source line represents a dot product multiplication of the data vector of the NVM storage string circuit coupled to the source line, by the input vector.

26. The method of claim 23, further comprising generating a plurality of currents flowing through each source line among the plurality of sources lines to a respective output node coupled to a respective NVM storage string circuits among the plurality of NVM storage string circuits based on a voltage applied to the bit line coupled to the respective NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the respective NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits in the respective NVM storage string circuit.

27. The method of claim 23, further comprising:

applying a line voltage to a bit line among the plurality of bit lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits;

applying a second line voltage to a source line among the plurality of source lines coupled to the corresponding NVM storage string circuit; and

applying a write activation voltage to the gate node of the NVM bit cell circuit in the corresponding NVM storage string circuit to write a memory state based on the write activation voltage applied to the gate node of the NVM bit cell circuit.

28. A non-volatile (NV) memory (NVM) matrix system, comprising:

a first NVM matrix circuit, comprising;

a plurality of first word lines configured to receive a first input vector represented by a first input voltage on each first word line among the plurality of first word lines;

a plurality of first bit lines, each first bit line among the plurality of first bit lines configured to receive a corresponding first line voltage;

a plurality of first source lines each coupled to a first output node among a plurality of first output nodes;

a plurality of first NVM storage string circuits, each first NVM storage string circuit among the plurality of first NVM storage string circuits configured to be electrically coupled between a corresponding first bit line among the plurality of first bit lines and a corresponding first source line among the plurality of first source lines, each comprising a plurality of first NVM bit cell circuits;

each first NVM bit cell circuit among the plurality of first NVM bit cell circuits having a resistance representing a stored memory state in the first NVM bit cell circuit to form a first data vector for the corresponding first NVM storage string circuit; and

each first NVM bit cell circuit among the plurality of first NVM bit cell circuits in the first NVM storage string circuit, comprising;

a first gate node coupled to a corresponding first word line among the plurality of first word lines; and

each first NVM bit cell circuit configured to couple its resistance to the first source line in response to the first input voltage applied to the corresponding first word line coupled to the first gate node; and

a second NVM matrix circuit, comprising;

a plurality of second word lines each coupled to an output node among the plurality of first output nodes;

a plurality of second bit lines, each second bit line among the plurality of second bit lines configured to receive a corresponding second line voltage;

a plurality of second source lines each coupled to a second output node among a plurality of second output nodes; and

a plurality of second NVM storage string circuits, each second NVM storage string circuit among the plurality of second NVM storage string circuits configured to be electrically coupled between a corresponding second bit line among the plurality of second bit lines and a corresponding second source line among the plurality of second source lines, each comprising a plurality of second NVM bit cell circuits;

each second NVM bit cell circuit among the plurality of second NVM bit cell circuits having a resistance representing a stored memory state in the second NVM bit cell circuit to form a second data vector for the corresponding second NVM storage string circuit; and

each second NVM bit cell circuit among the plurality of second NVM bit cell circuits in the second NVM storage string circuit, comprising;

a second gate node coupled to a corresponding second word line among the plurality of second word lines; and

each second NVM bit cell circuit configured to couple its resistance to the second source line in response to a second input voltage applied to the corresponding second word line coupled to the second gate node.

29. The NVM matrix system of claim 28, wherein:

the first NVM matrix circuit further comprises a plurality of first access transistors, each first access transistor among the plurality of first access transistors coupled to a corresponding first bit line among the plurality of first bit lines and a corresponding first NVM storage string circuit among the plurality of first NVM storage string circuits coupled to the first source line corresponding to the first bit line;

each first access transistor among the plurality of first access transistors comprising a first access gate node coupled to a first access line; and

each first access transistor among the plurality of first access transistors configured to electrically couple the corresponding first bit line to the corresponding first NVM storage string circuit in response to a first access voltage applied to the first access gate node; and

the second NVM matrix circuit further comprises a plurality of second access transistors, each second access transistor among the plurality of second access transistors coupled to a corresponding second bit line among the plurality of second bit lines and a corresponding second NVM storage string circuit among the plurality of second NVM storage string circuits coupled to the second source line corresponding to the second bit line;

each second access transistor among the plurality of second access transistors comprising a second access gate node coupled to a second access line; and

each second access transistor among the plurality of second access transistors configured to electrically couple the corresponding second bit line to the corresponding second NVM storage string circuit in response to a second access voltage applied to the second access gate node.

30. The NVM matrix system of claim 28, wherein:

a first NVM storage string circuit among the plurality of first NVM storage string circuits is configured to generate a respective first current flowing through the first source line among the plurality of first source lines coupled to the first NVM storage string circuit to a respective first output node based on the first line voltage applied to the first bit line coupled to the first NVM storage string circuit and the resistances applied by each of the plurality of first NVM bit cell circuits of the first NVM storage string circuit in response to a first read activation voltage being applied to the first gate nodes of each of the plurality of first NVM bit cell circuits; and

a second NVM storage string circuit among the plurality of second NVM storage string circuits is configured to generate a respective second current flowing through the second source line among the plurality of second source lines coupled to the second NVM storage string circuit to a respective second output node based on the second line voltage applied to the second bit line coupled to the second NVM storage string circuit and the resistances applied by each of the plurality of second NVM bit cell circuits of the second NVM storage string circuit in response to a second read activation voltage being applied to a first output node among the plurality of first output nodes of the first NVM matrix circuit coupled to the second gate nodes of each of the plurality of second NVM bit cell circuits.