MULTIPLE (MULTI-) LEVEL CELL (MLC) NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS WITH MULTI-BIT INPUT VECTORS
First Claim
1. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:
- a plurality of word lines configured to receive a multi-bit input vector represented by an input voltage on each word line among the plurality of word lines;
a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;
a plurality of source lines; and
a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of MLC NVM storage circuits; and
each MLC NVM storage circuit among the plurality of MLC NVM storage circuits comprising a plurality of NVM bit cell circuits each configured to store a respective memory state for the corresponding MLC NVM storage circuit;
each NVM bit cell circuit among the plurality of NVM bit cell circuits in a respective MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;
a gate node coupled to a corresponding word line among the plurality of word lines; and
each NVM bit cell circuit configured to couple its resistance to a source line among the plurality of source lines coupled to its respective MLC NVM storage circuit in response to the input voltage applied to the corresponding word line coupled to the gate node.
1 Assignment
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Accused Products
Abstract
Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.
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Citations
30 Claims
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1. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:
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a plurality of word lines configured to receive a multi-bit input vector represented by an input voltage on each word line among the plurality of word lines; a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage; a plurality of source lines; and a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of MLC NVM storage circuits; and each MLC NVM storage circuit among the plurality of MLC NVM storage circuits comprising a plurality of NVM bit cell circuits each configured to store a respective memory state for the corresponding MLC NVM storage circuit; each NVM bit cell circuit among the plurality of NVM bit cell circuits in a respective MLC NVM storage circuit having a resistance representing a stored memory state, and comprising; a gate node coupled to a corresponding word line among the plurality of word lines; and each NVM bit cell circuit configured to couple its resistance to a source line among the plurality of source lines coupled to its respective MLC NVM storage circuit in response to the input voltage applied to the corresponding word line coupled to the gate node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:
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a plurality of means for applying a plurality of input voltages representing a multi-bit input vector; a plurality of means for applying a plurality of line voltages; a plurality of means for providing a plurality of output currents representing an output vector; and a plurality of NVM storage string means each electrically coupled to a corresponding means for applying an input voltage among the plurality of means for applying the plurality of input voltages and a corresponding means for providing an output current among the plurality of means for providing the plurality of output currents, each of the plurality of NVM storage string means, comprising; a plurality of MLC NV means for storing a multi-bit memory state and each having a resistance representing the stored multi-bit memory state to form a data vector for a corresponding NVM storage string means among the plurality of NVM storage string means; and each of the plurality of MLC NV means for storing the multi-bit memory state, comprising; a means for electrically coupling a resistance of a plurality of NV bit means for storing a 1-bit memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents; and a means for controlling coupling of the resistance of the plurality of NV bit means for storing the 1-bit memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents.
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25. A method of performing matrix multiplication in a multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit, comprising:
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applying a line voltage on at least one bit line among a plurality of bit lines coupled to a corresponding NVM storage string circuit among a plurality of NVM storage string circuits, to electrically couple the line voltage to the corresponding NVM storage string circuit coupled to a corresponding bit line among the plurality of bit lines, each NVM storage string circuit among the plurality of NVM storage string circuits comprising a plurality of MLC NVM storage circuits each having a resistance representing a stored multi-bit memory state in the MLC NVM storage circuit to form a data vector for the corresponding NVM storage string circuit; applying a second line voltage on at least one source line among a plurality of source lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits, to electrically couple the second line voltage to the corresponding NVM storage string circuit coupled to a corresponding source line among the plurality of source lines; and applying a plurality of input voltages representing a multi-bit input vector on a plurality of word lines, each word line among the plurality of word lines coupled to a corresponding gate node of an NVM bit cell circuit among a plurality of NVM bit cell circuits in each MLC NVM storage circuit among the plurality of MLC NVM storage circuits in each NVM storage string circuit, to electrically couple the MLC NVM storage circuit to the source line to couple the resistance of the MLC NVM storage circuit to the source line. - View Dependent Claims (26, 27, 28, 29)
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30. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix system, comprising:
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a first MLC NVM matrix circuit, comprising; a plurality of first word lines configured to receive a first multi-bit input vector represented by a first input voltage on each first word line among the plurality of first word lines; a plurality of first bit lines, each first bit line among the plurality of first bit lines configured to receive a corresponding first line voltage; a plurality of first source lines each coupled to a first output node among a plurality of first output nodes; a plurality of first NVM storage string circuits, each first NVM storage string circuit among the plurality of first NVM storage string circuits configured to be electrically coupled between a corresponding first bit line among the plurality of first bit lines and a corresponding first source line among the plurality of first source lines each comprising a plurality of first MLC NVM storage circuits; each first MLC NVM storage circuit among the plurality of first MLC NVM storage circuits comprising a plurality of first NVM bit cell circuits each configured to store a respective memory state for the corresponding first MLC NVM storage circuit; each first NVM bit cell circuit among the plurality of first NVM bit cell circuits in a respective first MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;
a first gate node coupled to a corresponding first word line among the plurality of first word lines; andeach first NVM bit cell circuit configured to couple its resistance to the first source line coupled to its respective first MLC NVM storage circuit in response to an input voltage applied to the corresponding first word line coupled to the first gate node; and a second MLC NVM matrix circuit, comprising; a plurality of second word lines each coupled to an output node among the plurality of first output nodes; a plurality of second bit lines, each second bit line among the plurality of second bit lines configured to receive a corresponding second line voltage; a plurality of second source lines each coupled to a second output node among a plurality of second output nodes; and a plurality of second NVM storage string circuits, each second NVM storage string circuit among the plurality of second NVM storage string circuits configured to be electrically coupled between a corresponding second bit line among the plurality of second bit lines and a corresponding second source line among the plurality of second source lines each comprising a plurality of second MLC NVM storage circuits; each second MLC NVM storage circuit among the plurality of second MLC NVM storage circuits comprising a plurality of second NVM bit cell circuits each configured to store a respective memory state for the corresponding second MLC NVM storage circuit; each second NVM bit cell circuit among the plurality of second NVM bit cell circuits in a respective second MLC NVM storage circuit having a resistance representing a stored memory state, and comprising;
a second gate node coupled to a corresponding second word line among the plurality of second word lines; andeach second NVM bit cell circuit configured to couple its resistance to the second source line coupled to its respective second MLC NVM storage circuit in response to the input voltage applied to the corresponding second word line coupled to the second gate node.
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Specification