SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20190019869A1
• Filed: 02/04/2018
• Published: 01/17/2019
• Est. Priority Date: 07/12/2017
• Status: Abandoned Application

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Super Group Semiconductor Co., Ltd.
• Inventors: HSU, Hsiu-Wen, YEH, Chun-Ying, LO, Cheng-Ta, LEE, Yuan-Ming
• Application Number:
  US15/888,074
• Publication Number:
  US 20190019869A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a semiconductor device includes the following steps. An epitaxial layer is formed on a substrate. Then, a body is formed in an upper portion of the epitaxial layer. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed on the epitaxial layer. The third dielectric layer forms a second trench, and the second trench is located in the first trench. A shield layer is formed in the second trench. The upper portion of the third dielectric layer is removed, such that the upper portion of the shield layer protrudes from the third dielectric layer. A fourth dielectric layer is formed to cover the upper portion of the shield layer. A gate is formed on the third dielectric layer. A source is formed in the epitaxial layer surrounding the gate.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

forming an epitaxial layer on a substrate;

forming a body in an upper portion of the epitaxial layer;

forming a first trench in the epitaxial layer;

forming a first dielectric layer, a second dielectric layer, and a third dielectric layer on the epitaxial layer sequentially, wherein the third dielectric layer defines a second trench, and the second trench is located within the first trench;

forming a shield layer in the second trench;

removing an upper portion of the third dielectric layer, such that an upper portion of the shield layer is protruded from the third dielectric layer;

forming a fourth dielectric layer covering the upper portion of the shield layer;

forming a gate on the third dielectric layer; and

forming a source in the epitaxial layer surrounding the gate.

2. The method for manufacturing the semiconductor device of claim 1, wherein the forming the fourth dielectric layer comprises:

performing a thermal oxidation process to the shield layer to form the fourth dielectric layer.

3. The method for manufacturing the semiconductor device of claim 1, wherein a level of a top surface of the shield layer is between a level of a top surface of the body and a level of a bottom surface of the body.

4. The method for manufacturing the semiconductor device of claim 1, further comprising:

removing an upper portion of the second dielectric layer before forming the gate on the third dielectric layer.

5. The method for manufacturing the semiconductor device of claim 1, wherein a level of a top surface of the fourth dielectric layer is higher than a level of a top surface of the epitaxial layer.

6. A semiconductor device, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a body disposed on an upper portion of the epitaxial layer;

a third dielectric layer disposed in a first trench of the epitaxial layer and defining a second trench;

a shield layer having an upper portion and a lower portion, wherein the lower portion is located in the second trench, and the upper portion is protruded from the third dielectric layer;

a fourth dielectric layer covering the upper portion of the shield layer;

a gate disposed in the epitaxial layer and on the third dielectric layer, wherein at least a part of the fourth dielectric layer is disposed between the upper portion of the shield layer and the gate; and

a source disposed in the epitaxial layer surrounding the gate.

7. The semiconductor device of claim 6, wherein at least a part of the gate is disposed above the upper portion of the shield layer.

8. The semiconductor device of claim 6, further comprising:

a first dielectric layer disposed between the epitaxial layer and the third dielectric layer, wherein the first dielectric layer comprises silicon oxide; and

a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, wherein the second dielectric layer comprises silicon nitride.

9. The semiconductor device of claim 6, wherein the third dielectric layer comprises tetraethoxysilane (TEOS), and the fourth dielectric layer is formed by thermal oxidizing the shield layer.

10. The semiconductor device of claim 6, wherein a level of a top surface of the shield layer is between a level of a top surface of the body and a level of a bottom surface of the body.

11. The semiconductor device of claim 6, wherein a level of a top surface of the fourth dielectric layer is higher than a level of a top surface of the epitaxial layer.