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SELECTIVE INSERTION OF A DEADLOCK RECOVERY BUFFER IN A BUS INTERCONNECT FOR DEADLOCK RECOVERY

  • US 20190020586A1
  • Filed: 07/14/2017
  • Published: 01/17/2019
  • Est. Priority Date: 07/14/2017
  • Status: Abandoned Application
First Claim
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1. A deadlock recovery circuit for a bus interconnect, comprising:

  • a bus interconnect input interface configured to receive input bus transaction messages from a first router circuit in a bus interconnect, each of the input bus transaction messages comprising a data packet;

    a bus interconnect output interface configured to receive output bus transaction messages each comprising a data packet from the received input bus transaction messages to be forwarded to a second router circuit in the bus interconnect; and

    a deadlock recovery buffer configured to store at least one data packet;

    the deadlock recovery circuit configured to;

    receive the input bus transaction messages on the bus interconnect input interface;

    forward the output bus transaction messages on the bus interconnect output interface, each of the output bus transaction messages comprising at least one data packet from the received input bus transaction messages;

    detect a deadlock condition in the bus interconnect; and

    in response to the detected deadlock condition in the bus interconnect indicating a deadlock state, selectively communicatively couple the deadlock recovery buffer to the bus interconnect output interface.

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