MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

• US 20190026046A1
• Filed: 02/12/2018
• Published: 01/24/2019
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Kwang Su
• Granted Patent: US 10,445,021 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port

Abstract

Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

Claims

1. A method of operating a memory system, comprising:

receiving a first program command, and performing an operation corresponding to the first program command;

receiving a second program command while performing the operation corresponding to the first program command;

delaying setting of a queue status register for the second program command by a first wait time;

receiving a third read command before the first wait time elapses; and

setting the queue status register for the third read command before setting the queue status register for the second program command.

2. The method according to claim 1, further comprising performing, after the operation corresponding to the first program command is completed, an operation corresponding to the third read command based on a set status of the queue status register, and clearing the queue status register.

3. The method according to claim 2, further comprising delaying, after the queue status register is cleared, setting of the queue status register for the second program command until a second wait time elapses.

4. The method according to claim 2, further comprising setting, after the queue status register is cleared, the queue status register for the second program command.

5. The method according to claim 3, further comprising:

receiving a fourth read command before the second wait time elapses; and

setting the queue status register for the fourth read command before setting the queue status register for the second program command.

6. The method according to claim 3, wherein the second wait time is shorter than the first wait time.

7. The method according to claim 3, further comprising setting, when the queue status register is cleared after the second wait time has elapsed, the queue status register for the second program command.

8. The method according to claim 1, further comprising:

clearing the queue status register for the first program command,

wherein the first wait time starts from a time at which the queue status register for the first program command is cleared.

9. The method according to claim 7, further comprising:

receiving, after setting the queue status register for the second program command, a fourth read command; and

performing, after the operation corresponding to the third read command is completed, an operation corresponding to the second program command based on a set status of the queue status register.

10. The method according to claim 9, further comprising setting, after the queue status register for the second program command is cleared, the queue status register for the fourth read command without having a wait time.

11. The method according to claim 2, further comprising:

receiving, after the first wait time has elapsed, a fourth read command before the operation corresponding to the first program command is completed; and

setting, after the queue status register for the third read command is cleared, the queue status register for the second program command without having a wait time.

12. The method according to claim 2, further comprising:

receiving, after the first wait time has elapsed, a fourth read command before the operation corresponding to the first program command is completed; and

setting, after the queue status register for the third read command is cleared, the queue status register for the fourth read command without having a wait time.

13. A method of operating a memory system, comprising:

receiving a second program command while performing an operation corresponding to a first program command;

delaying setting of a queue status register for the second program command until a first wait time elapses;

receiving a third read command before the first wait time elapses;

setting the queue status register for the third read command before setting the queue status register for the second program command;

after the operation corresponding to the first program command is completed, starting an operation corresponding to the third read command based on a set status of the queue status register; and

after the operation corresponding to the third read command has started, delaying setting of the queue status register for the second program command until a second wait time elapses.

14. The method according to claim 13, further comprising setting, when a new read command is not inputted from a host before the second wait time elapses, the queue status register for the second program command after the second wait time has elapsed.

15. The method according to claim 13,

further comprising clearing the queue status register for the first program command,

wherein the first wait time starts from a time at which the queue status register for the first program command is cleared.

16. A memory system, comprising:

a memory device; and

a memory controller,

wherein the memory controller is configured to delay, when a first command is received from a host, setting of a queue status register for the first command by a predetermined wait time.

17. The memory system according to claim 16, wherein the first command is a program command.

18. The memory system according to claim 17, wherein the memory controller is configured to set, when a second command is inputted from the host before the wait time elapses, the queue status register for the second command before setting the queue status register for the first command.

19. The memory system according to claim 18, wherein the second command is a read command.

20. The memory system according to claim 16, wherein the memory controller controls the memory device based on a set status of the queue status register.