DISPLAY SUBSTRATE COMPRISING INTERCONNECTED FIRST AND SECOND WIRINGS AND DISPLAY DEVICE INCLUDING THE SAME

• US 20190027502A1
• Filed: 09/25/2018
• Published: 01/24/2019
• Est. Priority Date: 10/14/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Display Company Limited (Samsung Group)
• Inventors: Park, Ji-Yong, Kim, Tae-Gon
• Granted Patent: US 11,011,552 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

Claims

1. A method of manufacturing a display substrate, comprising:

forming a first semiconductor layer on a base substrate;

forming a first gate insulation layer to cover the first semiconductor layer on the base substrate;

forming a gate electrode and a first wiring on the first gate insulation layer;

forming a second gate insulation layer to cover the gate electrode and the first wiring;

forming a second wiring on the second gate insulation layer, the second wiring being formed over the first wiring and electrically connected to the first wiring; and

forming a source electrode and a drain electrode, the source and drain electrodes being electrically connected, through the second and first gate insulation layers, to the first semiconductor layer.

2. The method of claim 1, wherein the gate electrode and the first wiring are formed by the same etching process.

3. The method of claim 1, further comprising:

forming a lower electrode on the first gate insulation layer, and

forming an upper electrode on the second gate insulation layer, the upper electrode being formed over the lower electrode,

wherein the lower electrode, the gate electrode and the first wiring are formed by the same etching process, and wherein the upper electrode and the second wiring are formed by the same etching process.

4. The method of claim 1, wherein forming the second wiring includes:

partially

removing the second gate insulation layer to form a contact hole to at least partially expose the first wiring;

forming a conductive layer on the second gate insulation layer to fill the contact hole; and

patterning the conductive layer to form the second wiring.

5. The method of claim 1, further comprising forming a via structure to electrically connect the first and second wirings to each other.

6. The method of claim 5, wherein the via structure is formed simultaneously with the source electrode and the drain electrode.

7. The method of claim 6, further comprising:

forming an insulating interlayer covering the second wiring on the second gate insulation layer;

partially removing the insulating interlayer, the second gate insulation layer and the first gate insulation layer to form first openings that expose the first semiconductor layer;

partially removing the insulating interlayer and the second gate insulation layer to form a second opening that partially exposes the second wiring and the first wiring;

forming a conductive layer on the insulating interlayer to fill the first and second openings; and

patterning the conductive layer to form the source electrode, the drain electrode and the via structure.

8. The method of claim 7, wherein the first openings and the second opening are formed by the same etching process.