MULTI-SWITCH VOLTAGE REGULATOR

• US 20190028018A1
• Filed: 07/19/2018
• Published: 01/24/2019
• Est. Priority Date: 07/20/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: DATTA, Kishalay, MENEZES, Vinod
• Granted Patent: US 10,978,944 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/00 Conversion of dc power input into dc power output
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some examples, a voltage regulator includes a first pair of switches controllable by a first clock signal having a first phase. The switches in the first pair are coupled to each other via a capacitor. The voltage regulator also includes a second pair of switches controllable by a second clock signal having a second phase. The first and second phases are non-overlapping. The switches in the second pair are coupled to each other via the capacitor.

Claims

1. A voltage regulator comprising:

a first pair of switches controllable by a first clock signal having a first phase, the switches in the first pair being coupled to each other via a capacitor; and

a second pair of switches controllable by a second clock signal having a second phase that is non-overlapping with the first phase, and the switches in the second pair being coupled to each other via the capacitor.

2. The voltage regulator of claim 1, wherein a first switch in the first pair couples to a second switch in the second pair without intervening circuit components.

3. The voltage regulator of claim 1, wherein the capacitor is a first capacitor, and the voltage regulator further comprises:

a third pair of switches controllable by the second clock signal having the second phase, the switches in the third pair being coupled to each other via a second capacitor;

a fourth pair of switches controllable by the first clock signal having the first phase, the switches in the fourth pair being coupled to each other via the second capacitor,

wherein an arrangement of the third and fourth pairs with respect to the second capacitor is different than an arrangement of the first and second pairs with respect to the first capacitor.

4. The voltage regulator of claim 3, further comprising a decoupling capacitor, wherein the decoupling capacitor is coupled to the second capacitor when:

the first clock signal is asserted; and

the second clock signal is non-asserted.

5. The voltage regulator of claim 4, wherein the decoupling capacitor is coupled to the first capacitor when:

the second clock signal is asserted; and

the first clock signal is non-asserted.

6. The voltage regulator of claim 3, wherein at least one of the first and second pairs is coupled to at least one of the third and fourth pairs at a common node.

7. The voltage regulator of claim 3, wherein a switch in at least one of the first and second pairs is coupled to a voltage supply rail, and a switch in at least one of the third and fourth pairs is coupled to the voltage supply rail.

8. A system comprising:

a first unit cell comprising first switches to couple a first capacitor to outputs of the first unit cell in differing arrangements based on a trio of clock signals having non-overlapping phases;

a second unit cell comprising second switches to couple a second capacitor to outputs of the second unit cell in differing arrangements based on the trio of clock signals, wherein an arrangement of the second switches with respect to the second capacitor is different than an arrangement of the first switches with respect to the first capacitor;

a third unit cell comprising third switches to couple a third capacitor to outputs of the third unit cell in differing arrangements based on the trio of clock signals, wherein an arrangement of the third switches with respect to the third capacitor is different than the arrangement of the first switches with respect to the first capacitor and is different than the arrangement of the second switches with respect to the second capacitor; and

a load assembly to configure loads to receive power from the first, second and third unit cells, based on an enabled mode of the system.

9. The system of claim 8, wherein the first switches include first, second and third pairs of switches, the first pair being controlled by a first clock signal of the trio of clock signals having a first phase, and the switches in the first pair being coupled to each other via the first capacitor.

10. The system of claim 9, wherein the second pair is controlled by a second clock signal of the trio of clock signals having a second phase, and the switches in the second pair are coupled to each other via the first capacitor.

11. The system of claim 8, further comprising:

a voltage supply rail switchably coupled to the first, second and third unit cells and switchably coupled to one of a trio of decoupling capacitors; and

a linear regulator coupled to the voltage supply rail.

12. The system of claim 11, wherein the linear regulator is enabled based on a mode signal, and the mode signal is usable to determine which of the first, second and third unit cells is disabled.

13. The system of claim 12, further comprising logic to receive inputs based on multiple mode signals including the mode signal, and to activate and deactivate the second unit cell based on the inputs.

14. The system of claim 8, wherein the load assembly comprises fourth switches coupled to one or more of the loads.

15. The system of claim 14, wherein the fourth switches are controllable by mode signals.

16. A method comprising:

switchably coupling a first capacitor to a pair of decoupling capacitors via first and second pairs of switches;

switchably coupling a second capacitor to the pair of decoupling capacitors via third and fourth pairs of switches;

controlling the first and second pairs of switches using first and second clock signals having non-overlapping phases; and

controlling the third and fourth pairs of switches, using the first and second clock signals, to couple the first and second capacitors to different ones of the decoupling capacitors.

17. The method of claim 16, further comprising charging the first capacitor while discharging the second capacitor.

18. The method of claim 16, further comprising charging the first capacitor by a first amount in a clock cycle, and discharging the first capacitor by the first amount in another clock cycle.

19. The method of claim 16, further comprising removing a power supply rail connection to the second capacitor based on a selected mode.

20. The method of claim 16, further comprising adjusting a number of voltage domains supplied by the first, second, third and fourth pairs of switches based on an enabled mode.