HYBRID PHASE-LOCKED LOOP

• US 20190028108A1
• Filed: 07/18/2017
• Published: 01/24/2019
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Gao, Zhuo, Pandita, Bupesh, Hailu, Eskinder
• Granted Patent: US 10,355,702 B2
• Time in Patent Office: Days
• CPC Class Codes: H03D 3/24 Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A hybrid PLL is provided that includes an digital integral path and an analog proportional path.

Claims

1. A phase-locked loop (PLL), comprising:

a phase detector configured to assert an up signal in response to a reference signal leading a feedback signal and to assert a down signal in response to the feedback signal leading the reference signal;

a time-to-digital converter configured to convert a phase difference between the assertion of the up signal and the assertion of the down signal into a digital code;

a digital filter configured to integrate the digital code into an integrated digital code;

a delta-sigma modulator configured to modulate the integrated digital code into a modulated digital code;

an integral digital-to-analog converter configured to convert the modulated digital code into an analog integral control signal;

a proportional digital-to-analog converter configured to convert the up signal and the down signal into an analog proportional control signal; and

an oscillator configured to produce a PLL output signal responsive to the analog proportional control signal and to the analog integral control signal.

2. The PLL of claim 1, further comprising;

a frequency divider configured to divide the PLL output signal to produce the feedback signal.

3. The PLL of claim 1, wherein the time-to-digital converter includes an arbiter that produces a sign signal, a start signal, and a stop signal responsive to the phase difference between the up signal and the down signal.

4. The PLL of claim 3, wherein the time-to-digital converter includes a ring oscillator configured to oscillate responsive to an assertion of the start signal and to stop oscillating responsive to an assertion of the stop signal.

5. The PLL of claim 4, wherein the time-to-digital converter includes a set of registers configured to register a digital word responsive to the oscillation of the oscillator, and wherein the time-to-digital converter is configured to offset the digital word by an offset to form the digital code.

6. The PLL of claim 5, wherein the offset is a positive offset.

7. The PLL of claim 3, wherein the arbiter includes a cross-coupled pair of NAND gates configured to latch the sign signal.

8. The PLL of claim 7, wherein the arbiter includes a first inverter configured to invert the up signal into an input signal for a first NAND gate in the cross-coupled pair of NAND gates, and wherein the arbiter further includes a second inverter configured to invert the down signal into an input signal for a second NAND gate in the cross-coupled pair of NAND gates.

9. The PLL of claim 8, wherein the input signal to the first NAND gate drives a gate of a first NMOS transistor coupled between a ground node for the first inverter and ground.

10. The PLL of claim 9, wherein the input signal to the second NAND gate drives a gate of a second NMOS transistor coupled between a ground node for the first inverter and ground.

11. The PLL of claim 7, wherein the arbiter includes a third NAND gate configured to NAND the down signal with an inverted version of the up signal, and wherein an output of the third NAND gate is connected to an input for a first NAND gate in the cross-coupled pair of NAND gates.

12. The PLL of claim 11, wherein the arbiter further includes a fourth NAND gate configured to NAND the up signal with an inverted version of the down signal, and wherein an output of the fourth NAND gate is connected to an input for a second NAND gate in the cross-coupled pair of NAND gates.

13. The PLL of claim 7, wherein the arbiter further includes an OR gate configured to OR the up signal with the down signal to produce the start signal, and wherein the arbiter further includes an AND gate configured to AND the up signal with the down signal to produce the stop signal.

14. A method of phase-locking an output signal to a reference signal, comprising;

converting a phase difference between an up signal and a down signal into a digital code;

integrating the digital code to produce an integrated digital code;

delta-sigma modulating the integrated digital code to produce a modulated digital code;

converting the modulated digital code into an analog integral control signal;

converting the up signal and the down signal into an analog proportional control signal;

controlling an oscillator responsive to the analog integral control signal and the analog proportional control signal to produce the output signal.

15. The method of claim 14, further comprising:

dividing the output signal in frequency to produce a divided signal;

asserting the up signal responsive to the reference signal leading the divided signal; and

asserting the down signal responsive to the divided signal leading the reference signal.

16. The method of claim 14. wherein converting the phase difference between the up signal and the down signal comprises:

converting the phase difference into a digital word; and

offsetting the digital word by an offset to produce the digital code.

17. The method of claim 16, further comprising:

asserting a sign signal responsive to whether the up signal leads the down signal, wherein a positive or negative sign of the digital code equals the sign signal.

18. A phase-locked loop (PLL), comprising:

a phase detector configured to assert an up signal in response to a reference signal leading a feedback signal and to assert a down signal in response to the feedback signal leading the reference signal;

a time-to-digital converter configured to convert a phase difference between the assertion of the up signal and the assertion of the down signal into a digital word and to offset the digital word by an offset to produce a digital code;

means for integrating and converting the digital code to produce an analog integral control signal;

a proportional digital-to-analog converter configured to convert the up signal and the down signal into an analog proportional control signal;

a first current source configured to generate a first control current responsive to the analog integral control signal;

a second current source configured to generate a second control current responsive to the analog proportional control signal; and

a current-controlled oscillator configured to produce a PLL output signal responsive to the first control current and to the second control current.

19. The PLL of claim 18, wherein the time-to-digital converter further includes an arbiter configured to assert a sign signal responsive to whether the up signal leads the down signal.

20. The PLL of claim 19, wherein the time-to-digital converter includes a cross-coupled pair of NAND gates.