STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY POWER SUPPLY CIRCUIT

• US 20190035435A1
• Filed: 07/27/2018
• Published: 01/31/2019
• Est. Priority Date: 07/27/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: HUANG, Chen-Yi, YANG, Chia Chi, LUO, Dong Xiang, HUANG, Cheng-Tai
• Granted Patent: US 10,607,662 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A Static Random Access Memory (SRAM) array power supply circuit is presented. The circuit comprises an SRAM test unit having a substantially same structure as a basic SRAM unit in the SRAM array; a switch device connected to a power source, the SRAM test unit, and the SRAM array; and a switch control circuit connected to the SRAM test unit and the switch device. When a test voltage in the SRAM test unit is lower than a threshold voltage, the switch device is closed so that the power source begins to charge the SRAM array and the SRAM test unit. The SRAM test unit provides an early warning for the SRAM array, allowing the latter to be charged upon fulfillment of a condition (e.g., charge is low). Compared to conventional circuits, this circuit provides an output voltage that is more stable and less susceptible to the changes in external conditions such as temperature or pressure.

Claims

1. A Static Random Access Memory (SRAM) array power supply circuit, comprising:

an SRAM test unit having a substantially same structure as a basic SRAM unit in the SRAM array;

a switch device connected to a power source, the SRAM test unit, and the SRAM array; and

a switch control circuit connected to the SRAM test unit and the switch device, wherein when a test voltage in the SRAM test unit is lower than a threshold voltage, the switch device is closed so that the power source begins to charge the SRAM array and the SRAM test unit.

2. The circuit of claim 1, wherein when a leakage voltage in the SRAM test unit is higher than the threshold voltage, the switch control circuit opens the switch device so that the power source no longer charges the SRAM array and the SRAM test unit.

3. The circuit of claim 1, wherein a supply voltage to the SRAM test unit is less than a supply voltage to the SRAM array, wherein the supply voltage to the SRAM test unit or the SRAM array is a voltage at a source of a P-type Metal-Oxide-Semiconductor (PMOS) transistor in a basic SRAM unit in the SRAM test unit or in a basic SRAM unit in the SRAM array.

4. The circuit of claim 1, wherein at least one of the following three conditions are true:

(a) the SRAM test unit is a basic SRAM unit in the SRAM array;

(b) the SRAM test unit is a backup basic SRAM unit of the SRAM array;

(c) the SRAM test unit and the SRAM array are in a same environmental temperature.

5. The circuit of claim 1, wherein the power source is connected to the SRAM test unit and the SRAM array, and provides a minimum current to the SRAM test unit and the SRAM array.

6. The circuit of claim 1, further comprising:

a leakage acceleration circuit connected to the SRAM test unit and the switch control circuit, wherein the leakage acceleration circuit accelerates the current leakage in the SRAM test unit.

7. The circuit of claim 6, wherein the leakage acceleration circuit comprises Complementary Metal-Oxide-Semiconductor (CMOS) transistors.

8. The circuit of claim 1, wherein the switch control circuit is a buffer.

9. The circuit of claim 1, wherein the circuit is a low-voltage linear regulator.

10. The circuit of claim 1, wherein the switch device is an electric relay, a PMOS transistor, or an NMOS transistor.

11. The circuit of claim 1, wherein the switch device comprises a first switch connected to the power source and the SRAM test unit, and a second switch connected to the SRAM array and the first switch,

wherein the switch control circuit is connected to the first switch and the second switch, and wherein when the test voltage of the SRAM test unit is less than the threshold voltage, the first switch and the second switch are closed, so that the power source begins to charge the SRAM array and the SRAM test unit.

12. The circuit of claim 11, wherein at least one of the following two conditions are true:

(a) the first switch is an electric relay, a PMOS transistor, or an NMOS transistor;

(b) the second switch is an electric relay, a PMOS transistor, or an NMOS transistor.