Method and Apparatus for Providing Low Latency Solid State Memory Access

• US 20190035445A1
• Filed: 07/31/2017
• Published: 01/31/2019
• Est. Priority Date: 07/31/2017
• Status: Abandoned Application

• Current Assignee: Point Financial, Inc.
• Original Assignee: Cnex Labs, Inc.
• Inventors: Huang, Yiren Ronnie
• Application Number:
  US15/665,068
• Publication Number:
  US 20190035445A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

One embodiment of the present invention discloses a process of low latency non-volatile memory access using various approaches. In one aspect, a process for low latency memory access to a non-volatile memory (“NVM”) of a solid state drive (“SSD”) is able to generate a submission queue entry (“SQE”) for an SSD memory access by a host to a connected SSD. Upon pushing the SQE from the host to a submission queue (“SQ”) viewable by a controller of the SSD, the counter value of an SQ header pointer is incremented to reflect storage of the first SQE in the SQ. After detecting the SQE in the SQ by a snooping component in the memory controller in accordance with the SQ header pointer, the SQE is fetched from the SQ by the controller and one or more SSD memory instructions are subsequently executed in response to content of the SQE.

Claims

1. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via a memory controller snooping, comprising;

generating a first submission queue entry (“

SQE”

) for a first SSD memory access by a host to a connected SSD;

pushing the first SQE from the host to a submission queue (“

SQ”

) viewable by a controller of the SSD;

incrementing counter value of an SQ header pointer to reflect storage of the first SQE in the SQ;

detecting the first SQE in the SQ by a snooping component in the memory controller in accordance with the SQ header pointer; and

fetching the first SQE from the snooping component in the controller and executing one or more SSD memory instructions in response to content of the first SQE.

2. The method of claim 1, wherein detecting the first SQE in the SQ further includes identifying a difference between the SQ header pointer and an SQ tail pointer.

3. The method of claim 2, wherein pushing the first SQE from the host to a submission queue (“

SQ”

) includes storing the first SQE into the SQ via a Peripheral Component Interconnect Express (“

PCIe”

) bus connected between the host and the SSD.

4. The method of claim 3, further comprising:

generating a second SQE for a second SSD memory access by the host;

pushing the second SQE from the host to the SQ; and

incrementing counter value of the SQ header pointer to reflect storage of the second SQE in the SQ.

5. The method of claim 1, further comprising:

performing the first SSD memory access by the memory controller in accordance with the first SQE;

generating a first completion queue entry (“

CQE”

) in accordance with a first result of performance of the first SSD memory access; and

storing the first CQE by the memory controller to a completion queue (“

CQ”

) viewable by the host.

6. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via a host CPU polling, comprising;

performing a first SSD memory access by a controller of SSD in accordance with a first submission queue entry (“

SQE”

) generated by a connected host;

generating a first completion queue entry (“

CQE”

) in accordance with a first result of performance of the first SSD memory access;

storing the first CQE by the controller to a completion queue (“

CQ”

) viewable by the host;

periodically polling the CQ by the host to identify whether the first CQE is present in response to the first SEQ;

fetching the first CQE from the CQ upon detection of the first CQE by the host via a polling activity; and

obtaining by the host the first result of the performance based on the first CQE.

7. The method of claim 6, further comprising:

generating a first submission queue entry (“

SQE”

) for a first SSD memory access by a host to a connected SSD; and

pushing the first SQE from the host to a submission queue (“

SQ”

) viewable by the controller.

8. The method of claim 7, further comprising:

incrementing counter value of an SQ header pointer to reflect storage of the first SQE in the SQ; and

detecting the first SQE in the SQ by a snooping component in the memory controller in accordance with the SQ header pointer.

9. The method of claim 8, further comprising fetching the first SQE from the SQ by the controller and executing one or more SSD memory instructions based on content of the first SQE.

10. The method of claim 6, further comprising:

performing a second SSD memory access by a memory controller in accordance with a second SQE;

generating a second completion queue entry (“

CQE”

) in accordance with a second result of performance of the second SSD memory access; and

storing the second CQE by the memory controller to the CQ.

11. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via a cache content access, comprising;

receiving a first write command by a memory controller of SSD from a host for an SSD memory access;

confining writing process associated with the first write command to one (1) logic unit number (“

LUN”

) in an SSD at a given time for performing the first write command;

writing first content from the host to the LUN in accordance with the first write command;

caching the first content associated with the first write command to a cache while the first content is copied to the LUN; and

allowing the host to access the first content via the cache while the LUN is programmed for storing the first content. storing valid data during a process of garbage collection.

12. The method of claim 11, further comprising generating the first write command by the host for NVM storage access.

13. The method of claim 12, further comprising sending the first write command to the SSD via a Peripheral Component Interconnect Express (“

PCIe”

) bus.

14. The method of claim 11, wherein caching the first content associated with the first write command includes storing the first content in a snooping command cache located in a SSD controller.

15. The method of claim 11, wherein caching the first data content associated with the first write command includes storing the first content in a memory cache located in the controller.

16. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via an LUN block erasing process, comprising;

receiving a first write command by a memory controller from a host for an SSD memory access;

identifying a first logic unit number (“

LUN”

) in an SSD as a destination storage location for the first write command;

erasing all blocks within the first LUN; and

programming first content from the host to the first LUN in accordance with the first write command.

17. The method of claim 16, further comprising generating the first write command by the host for NVM storage access.

18. The method of claim 17, further comprising sending the first write command to the SSD via a Peripheral Component Interconnect Express (“

PCIe”

) bus.

19. The method of claim 16, wherein identifying a first logic unit number (“

LUN”

) in an SSD further includes determining the first LUN pointed by flash translation layer (“

FTL”

) table in response to the first write command.

20. The method of claim 16, wherein erasing all blocks within the first LUN includes moving valid pages in the first LUN to a second LUN during a process of garbage collection for recycling valid sectors on an old block in first LUN.

21. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via accessing erase-marked logic unit number (“

LUN”

), comprising;

receiving a memory command by a memory controller of SSD from a host for an SSD memory access;

identifying targeted LUN associated with the memory command in response to facilitation of a flash translation table (“

FTL”

);

determining whether the targeted LUN is busy in performing a garbage collection (“

GC”

) process with copying a set of valid pages from an erase-marked LUN to the targeted LUN; and

executing the memory commend in accordance with the erase-marked LUN while the GC process to the targeted LUN continues.

22. The method of claim 21, wherein receiving a memory command by a memory controller of SSD includes receiving one of a read command and a write command from a coupled system.

23. The method of claim 21, further comprising sending the command to the SSD via a Peripheral Component Interconnect Express (“

PCIe”

) bus.

24. A method for memory access to a non-volatile memory (“

NVM”

) solid state drive (“

SSD”

) via a temporarily parking process, comprising;

receiving a first submission queue entry (“

SQE”

) from a first submission queue (“

SQ”

) for a first SSD memory access by a host to an SSD;

identifying first LUN associated with the first SQE in accordance with facilitation of a flash translation table (“

FTL”

);

determining whether the first LUN is busy for performing scheduled tasks and identifying whether a first local temporarily parking lot (“

TPL”

) associated with the first LUN is full if the first LUN is busy; and

storing the first SQE in the first local TPL if the first local TPL is not full.

25. The method of claim 24, further comprising storing the first SQE in a global TPL if the first local TPL is full.

26. The method of claim 25, further comprising:

obtaining a second SQE from a second SQ for a second SSD memory access by the host; and

identifying second LUN associated with the second SQE memory in accordance with facilitation of the FTL.

27. The method of claim 26, further comprising:

determining whether the second LUN is busy for performing scheduled tasks and identifying whether a second LPL associated with the second LUN is full if the second LUN is busy; and

storing the second SQE in the second local TPL if the second local TPL is not full.

28. The method of claim 27, further comprising storing the second SQE in the global TPL if the second local TPL is full.

29. The method of claim 28, further comprising moving the second SQE from the global TPL to the second local TPL when the second local TPL becomes open.