MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20190035481A1
• Filed: 05/11/2018
• Published: 01/31/2019
• Est. Priority Date: 07/26/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Hae Soo
• Granted Patent: US 10,453,542 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

Provided herein may be a method of operating a memory device. The method may include applying an erase voltage to a memory block. The method may include performing an erase verify operation on the memory block. The method may include performing a first blind program operation based on a result of the erase verify operation.

Claims

1. A method of operating a memory device comprising:

applying an erase voltage to a memory block;

performing an erase verify operation on the memory block; and

performing a first blind program operation based on a result of the erase verify operation.

2. The method according to claim 1, wherein the first blind program operation is performed when the result of the erase verify operation indicates failure.

3. The method according to claim 2, wherein the first blind program operation is performed by simultaneously applying a first blind program voltage to a plurality of word lines coupled to the memory block.

4. The method according to claim 1, further comprising, before the applying of the erase voltage, performing a second blind program operation on the memory block.

5. The method according to claim 4, wherein the second blind program operation is performed regardless of whether a program operation has been performed on memory cells that are included in the memory block and coupled to a plurality of word lines.

6. The method according to claim 4, wherein the second blind program operation is performed regardless of whether memory cells, that are included in the memory block and coupled to a plurality of word lines, are in an erase state or a program state.

7. The method according to claim 4, wherein performing the second blind program operation on the memory block includes increasing threshold voltages of memory cells, that are included in the memory block and coupled to a plurality of word lines, having threshold voltages that are in an erase state.

8. The method according to claim 3, further comprising, after the first blind program operation has been performed:

changing the erase voltage;

applying the changed erase voltage to the memory block;

increasing the first blind program voltage; and

performing the first blind program operation using the changed first blind program voltage.

9. The method according to claim 3, further comprising, after the first blind program operation has been performed:

changing the erase voltage;

applying the changed erase voltage to the memory block; and

performing the first blind program operation using the first blind program voltage again.

10. The method according to claim 3, further comprising, after the first blind program operation has been performed:

changing the erase voltage;

applying the changed erase voltage to the memory block;

decreasing the first blind program voltage; and

performing the first blind program operation using the decreased first blind program voltage.

11. The method according to claim 2, further comprising performing a second blind program operation when the result of the erase verify operation indicates pass.

12. The method according to claim 11,

wherein the second blind program operation includes a plurality of blind program loops, and

wherein each of the blind program loops comprises a second blind program voltage application operation and a blind program verify operation.

13. The method according to claim 12, wherein the blind program verify operation comprises determining that the second blind program operation has passed, when the number of strings that are determined to be turned off is a predetermined value or more.

14. The method according to claim 13, wherein the blind program verify operation is successively performed on memory cells coupled to an even bit line and memory cells coupled to an odd bit line.

15. A method of operating a memory device comprising:

performing a first blind program operation on a memory block;

applying an erase voltage to the memory block;

performing an erase verify operation on the memory block; and

performing a second blind program operation on the memory block when a result of the erase verify operation indicates failure.

16. The method according to claim 15, further comprising, after the second blind program operation has been performed, increasing the erase voltage, and applying the increase erase voltage to the memory block.

17. The method according to claim 16,

wherein, after the applying of the increased erase voltage to the memory block, the erase verify operation is performed on the memory block again, and

wherein, when a result of the erase verify operation performed again indicates failure, the second blind program operation is performed again.

18. The method according to claim 17, wherein a voltage to be applied to a plurality of word lines coupled to the memory block during the second blind program operation is the same as a voltage to be applied to the word lines during the second blind program operation performed again.

19. A method of operating a memory device comprising:

applying an erase voltage to a memory block;

performing an erase verify operation on the memory block; and

performing either a first blind program operation or a second blind program operation on the memory block based on a result of the erase verify operation.

20. The method according to claim 19, wherein the first blind program operation is performed when the result of the erase verify operation indicates failure.

21. The method according to claim 20,

wherein the second blind program operation includes a blind program verify operation, and

wherein the blind program verify operation is performed by simultaneously applying a blind program verify voltage to a plurality of word lines coupled to the memory block.

22. The method according to claim 21,

wherein the erase verify operation is performed by simultaneously applying an erase verify voltage to the word lines, and

wherein the blind program verify voltage is different from the erase verify voltage.

23. A method of operating a memory device comprising:

applying an erase voltage to a memory block;

performing an erase verify operation on the memory block; and

performing a first blind program operation according to an erase count value of the memory block, based on a result of the erase verify operation.

24. The method according to claim 23, wherein the first blind program operation is performed when the result of the erase verify operation indicates failure, and when the erase count value is greater than a predetermined first threshold value.

25. The method according to claim 24, further comprising, before the applying of the erase voltage, performing a second blind program operation on the memory block when the erase count value is greater than a predetermined second threshold value.

26. The method according to claim 24, further comprising performing a second blind program operation when the result of the erase verify operation indicates pass, and when the erase count value is greater than a predetermined second threshold value.