INTEGRATED CIRCUIT SECURITY

• US 20190035746A1
• Filed: 07/27/2017
• Published: 01/31/2019
• Est. Priority Date: 07/27/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lai, Kafai, Topaloglu, Rasit O.
• Granted Patent: US 10,312,200 B2
• Time in Patent Office: Days
• CPC Class Codes: B65D 33/16 End- or aperture-closing arrangements or devices valves of valve bags B65D31/14 ; removable stoppers or caps B65D39/00, B65D41/00; closures of filled bags B65D77/10; closing filled bags in association with packaging B65B7/00, B65B51/00
• CPC Class Codes: B65D 33/28 Strings or strip-like closures , i.e. draw closures
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 21/67282 Marking devices
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H03K 19/195 using superconductive devices

Abstract

A semiconductor product includes a substrate having a self-assembly (SA) pattern. An initial SA pattern is created using a block copolymer (BCP) which has been annealed on the substrate. The initial SA pattern and/or an enlarged SA pattern derived from the initial SA pattern is incorporated into the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product. In other embodiments of the invention a method and system for creating the semiconductor product are described.

Claims

1. A semiconductor product comprising:

a substrate having a self-assembly (SA) pattern, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate, wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

2. The semiconductor product as recited in claim 1, wherein the substrate is a semiconductor chip and the initial SA pattern has been created on an upper, physically observable layer.

3. The semiconductor product as recited in claim 2, wherein the semiconductor chip is attached to a package so that the initial SA pattern is a physically observable security feature.

4. The semiconductor product as recited in claim 1, further comprising a package having an enlarged SA pattern, the enlarged SA pattern derived from the initial SA pattern, wherein the substrate is a semiconductor chip attached to the package.

5. The semiconductor product as recited in claim 4, wherein the package has an opening where the enlarged SA pattern is located and can be optically observed.

6. The semiconductor product as recited in claim 1, further comprising a package on which a semiconductor chip having an enlarged SA pattern is attached, the enlarged SA pattern derived from the initial SA pattern.

7. A method for manufacturing a semiconductor product comprising:

creating a self-assembly (SA) pattern on a substrate, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate;

scanning the SA pattern to capture an image of the SA pattern;

storing data from the SA pattern in a computer system; and

providing the SA pattern on the semiconductor product;

wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

8. The method as recited in claim 7, wherein the substrate is a semiconductor chip and the initial SA pattern has been created on an upper, physically observable layer.

9. The method as recited in claim 7, wherein the substrate is a semiconductor chip and the method further comprises:

generating an enlarged SA pattern from the SA pattern; and

creating the enlarged SA pattern on the semiconductor product.

10. The method as recited in claim 7, further comprising:

storing a set of features and feature locations within the SA pattern;

associating the set of features and feature locations with the semiconductor product.

11. The method as recited in claim 7, further comprising:

receiving a set of features and feature locations from a customer;

verifying the received set of features and feature locations as associated with the semiconductor product.

12. The method as recited in claim 10, wherein the set of features are selected from the group consisting of line end features, fork features and short-line features.

13. The method as recited in claim 11, wherein the set of features and feature locations are stored efficiently using a sparse matrix representation and wherein the received set of features and feature locations are used to verify a customer semiconductor product against a SA pattern database using an elastic string match utilizing an edit distance metric to compare the stored set of features and feature locations with the received set of features and feature locations.

14. The method as recited in claim 9, further comprising:

providing a first layer and a second layer on a semiconductor chip, wherein the second layer is disposed on top of the first layer and is selected to provide an optical contrast to the first layer;

providing a lithographic pattern on the second layer, the lithographic pattern a version of the enlarged SA pattern; and

etching through exposed portions of the second layer to create the enlarged SA pattern on the semiconductor chip.

15. Apparatus, comprising:

a processor;

a scanner;

a computer memory holding computer program instructions executed by the processor, the computer program instructions comprising;

program code, operative to receive an image of a self-assembly (SA) pattern on a substrate from the scanner, wherein the SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate;

program code, operative to store data from the SA pattern in a computer system; and

program code, operative to associate the SA pattern data with the semiconductor product;

wherein the SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

16. The apparatus recited in claim 15, wherein the substrate is a semiconductor chip and the computer program instructions further comprise:

program code, operative to generating an enlarged SA pattern from the SA pattern;

program code, operative to store SA pattern data about the enlarged SA pattern in the computer memory; and

program code, operative to associate the SA pattern data about the enlarged SA pattern with the semiconductor product.

17. The apparatus as recited in claim 15, wherein the SA pattern data is a set of features and feature locations from the SA image and the computer program instructions further comprise:

program code, operative to receive a set of features and feature locations from a customer;

program code, operative to verify the received set of features and feature locations as associated with the semiconductor product by matching the received set of features and feature locations with the stored features and feature locations.

18. The apparatus as recited in claim 15, wherein the scanner is a scanning electron microscope.

19. The apparatus as recited in claim 16, wherein the program code, operative to generating an enlarged SA pattern from the SA pattern further comprises:

program code, operative to invert the SA pattern image;

program code, operative to clarify scanned lines from the SA pattern image; and

program code, operative to add a registration mark to the enlarged SA pattern.

20. The apparatus as recited in claim 15 further comprising program code operative to associate the SA pattern data with model and serial numbers information.