SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20190035792A1
• Filed: 01/22/2018
• Published: 01/31/2019
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Original Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Inventors: Lu, Tsuo-Wen, Lin, Ger-Pin, Chan, Tien-Chen, Chan, Shu-Yen
• Granted Patent: US 10,373,958 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a gate trench comprised of an upper trench and a lower trench, wherein the upper trench is wider than the lower trench, wherein the upper trench and the lower trench are both located within the semiconductor substrate, and wherein the upper trench has a vertical sidewall;

a gate embedded in the gate trench, wherein the gate comprises an upper portion and a lower portion;

a first gate dielectric layer between the upper portion and the vertical sidewall of the upper trench, wherein the first gate dielectric layer has a first thickness; and

a second gate dielectric layer between the lower portion and a sidewall of the lower trench, wherein the second gate dielectric layer has a second thickness that is smaller than the first thickness.

2. The semiconductor device according to claim 1, wherein the gate has a uniform width throughout depth of the gate trench.

3. The semiconductor device according to claim 2, wherein the upper portion of the gate has a width that is equal to that of the lower portion of the gate.

4. The semiconductor device according to claim 1, wherein the gate trench has a trench width gradually decreased from its top to its bottom.

5. The semiconductor device according to claim 1, wherein the first gate dielectric layer comprises an atomic layer deposition (ALD) silicon oxide layer.

6. The semiconductor device according to claim 5, wherein the first thickness ranges between 60 and 80 angstroms.

7. The semiconductor device according to claim 1, wherein the second gate dielectric layer comprises an in-situ steam generation (ISSG) silicon oxide layer.

8. The semiconductor device according to claim 7, wherein the second thickness ranges between 40 and 60 angstroms.

9. The semiconductor device according to claim 1, wherein the first gate dielectric layer comprises a surface that is aligned with a surface of the second gate dielectric layer.

10. The semiconductor device according to claim 1, wherein the gate comprises a tungsten layer and TiN liner layer, wherein the TiN liner layer is disposed between the tungsten layer and the first gate dielectric layer and between the tungsten layer and the second gate dielectric layer.

11. A method for fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming an upper trench in the semiconductor substrate;

depositing a first gate dielectric layer on interior surface of the upper trench, wherein the first gate dielectric layer has a first thickness;

anisotropically etching the first gate dielectric layer and the semiconductor substrate, thereby forming a lower trench in a self-aligned manner, wherein the upper trench and the lower trench constitute a gate trench; and

thermally growing a second gate dielectric layer on interior surface of the lower trench, wherein the second gate dielectric layer has a second thickness, and the second thickness is less than the first thickness.

12. The method for fabricating a semiconductor device according to claim 11 further comprising:

forming a gate in the gate trench, wherein the gate comprises an upper portion and a lower portion.

13. The method for fabricating a semiconductor device according to claim 12, wherein the gate has a uniform width throughout depth of the gate trench.

14. The method for fabricating a semiconductor device according to claim 13, wherein the upper portion of the gate has a width that is equal to that of the lower portion of the gate.

15. The method for fabricating a semiconductor device according to claim 11, wherein the first gate dielectric layer is deposited by an atomic layer deposition (ALD) method.

16. The method for fabricating a semiconductor device according to claim 15, wherein the first thickness ranges between 60 and 80 angstroms.

17. The method for fabricating a semiconductor device according to claim 11, wherein the second gate dielectric layer is grown by an in-situ steam generation (ISSG) method.

18. The method for fabricating a semiconductor device according to claim 17, wherein the second thickness ranges between 40 and 60 angstroms.

19. The method for fabricating a semiconductor device according to claim 11, wherein the first gate dielectric layer comprises a surface that is aligned with a surface of the second gate dielectric layer.

20. The method for fabricating a semiconductor device according to claim 12, wherein the gate comprises a tungsten layer and TiN liner layer, wherein the TiN liner layer is disposed between the tungsten layer and the first gate dielectric layer and between the tungsten layer and the second gate dielectric layer.