METHODS AND APPARATUS TO COMPILE CODE TO GENERATE DATA FLOW CODE

• US 20190042217A1
• Filed: 12/27/2017
• Published: 02/07/2019
• Est. Priority Date: 12/27/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glossop, Kent, Fleming, Kermin, Zhang, Yongzhi, Steely, JR., Simon, Sukha, James, Srinivasan, Uma
• Granted Patent: US 10,402,176 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

Claims

1. A compiler apparatus comprising:

an intermediate representation transformer to transform input software code to intermediate representation code;

an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and

a target machine transformer to;

convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and

allocate registers within the dataflow intermediate representation code.

2. The compiler apparatus as defined in claim 1, wherein the target machine transformer includes a dataflow converter to convert the portion of the machine intermediate representation code to the dataflow code to generate the dataflow intermediate representation code.

3. The compiler apparatus as defined in claim 2, wherein the dataflow converter is to generate machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

4. The compiler apparatus as defined in claim 2, wherein the dataflow converter is to allocate latency insensitive channels to the machine intermediate representation code.

5. The compiler apparatus as defined in claim 2, wherein the dataflow converter is to select a first region of the machine intermediate representation code and to convert the first region to dataflow code prior to converting a second region, wherein the first region is contained within the second region.

6. The compiler apparatus as defined in claim 2, wherein the dataflow converter is to move operations converted to dataflow code onto dataflow units of the target execution platform.

7. The compiler apparatus as defined in claim 2, wherein the dataflow converter is to remove branches from the machine intermediate representation code.

8. A compiler apparatus as defined in claim 1, wherein the target execution platform is a spatial accelerator.

9. A non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least:

transform input software code to intermediate representation code;

insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code;

convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and

allocate registers within the dataflow intermediate representation code.

10. The non-transitory computer readable medium as defined in claim 9, wherein the instructions, when executed, cause the machine to convert the portion of the machine intermediate representation code to the dataflow code to generate the dataflow intermediate representation code.

11. The non-transitory computer readable medium as defined in claim 10, wherein the instructions, when executed, cause the machine to generate machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

12. The non-transitory computer readable medium as defined in claim 10, wherein the instructions, when executed, cause the machine to allocate latency insensitive channels to the machine intermediate representation code.

13. The non-transitory computer readable medium as defined in claim 10, wherein the instructions, when executed, cause the machine to select a first region of the machine intermediate representation code and to convert the first region to dataflow code prior to converting a second region, wherein the first region is contained within the second region.

14. The non-transitory computer readable medium as defined in claim 10, wherein the instructions, when executed, cause the machine to move operations converted to dataflow code onto dataflow units of the target execution platform.

15. The non-transitory computer readable medium as defined in claim 10, wherein the instructions, when executed, cause the machine to remove branches from the machine intermediate representation code.

16. The non-transitory computer readable medium as defined in claim 9, wherein the target execution platform is a spatial accelerator.

17. A method comprising:

transforming, by executing an instruction with a processor, input software code to intermediate representation code;

inserting, by executing an instruction with a processor, machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code;

converting, by executing an instruction with a processor, a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and

allocating, by executing an instruction with a processor, registers within the dataflow intermediate representation code.

18. The method as defined in claim 17, further including converting the portion of the machine intermediate representation code to the dataflow code to generate the dataflow intermediate representation code.

19. The method as defined in claim 18, further including generating machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

20. The method as defined in claim 18, further including allocating latency insensitive channels to the machine intermediate representation code.

21. The method as defined in claim 18, further including selecting a first region of the machine intermediate representation code and to convert the first region to dataflow code prior to converting a second region, wherein the first region is contained within the second region.

22. The method as defined in claim 18, further including moving operations converted to dataflow code onto dataflow units of the target execution platform.

23. The method as defined in claim 18, further including removing branches from the machine intermediate representation code.

24. The method as defined in claim 17, wherein the target execution platform is a spatial accelerator.