SEQUENCE OPTIMIZATIONS IN A HIGH-PERFORMANCE COMPUTING ENVIRONMENT
First Claim
1. An apparatus, comprising:
- memory to store executable computer program instructions; and
processing circuitry coupled with the memory, the processing circuitry operable to execute the instructions, that when executed, enable processing circuitry to;
determine dataflow graph instructions comprising one or more pick/switch instruction pairs;
generate a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs; and
traverse the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions.
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Abstract
Embodiments are directed to techniques to determine dataflow graph instructions comprising one or more pick/switch instruction pairs and generate a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs. Embodiments also include traversing the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions.
56 Citations
25 Claims
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1. An apparatus, comprising:
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memory to store executable computer program instructions; and processing circuitry coupled with the memory, the processing circuitry operable to execute the instructions, that when executed, enable processing circuitry to; determine dataflow graph instructions comprising one or more pick/switch instruction pairs; generate a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs; and traverse the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer-implemented method, comprising:
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determining dataflow graph instructions comprising one or more pick/switch instruction pairs; generating a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs; and traversing the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to:
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determine dataflow graph instructions comprising one or more pick/switch instruction pairs; generate a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs; and traverse the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification