ERROR CORRECTION CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME

• US 20190042360A1
• Filed: 03/27/2018
• Published: 02/07/2019
• Est. Priority Date: 08/03/2017
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SONG, Young-Ook
• Application Number:
  US15/936,684
• Publication Number:
  US 20190042360A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/153 using the Berlekamp-Massey algorithm
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
• CPC Class Codes: H03M 13/1575 Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing

Abstract

An error correction circuit includes: a syndrome calculation block suitable for generating a syndrome based on a data and an error correction code; an error location polynomial generation block suitable for generating an error location polynomial for detecting a location of an error based on the syndrome, where the number of operation stages used for generating the error location polynomial is controlled based on condition information; and a chien search block suitable for correcting an error of the data based on the error location polynomial.

Claims

1. An error correction circuit, comprising:

a syndrome calculation block suitable for generating a syndrome based on a data and an error correction code;

an error location polynomial generation block suitable for generating an error location polynomial for detecting one or more locations of one or more errors based on the syndrome, where a number of operation stages used for generating the error location polynomial is controlled based on a condition information; and

a chien search block suitable for correcting one or more errors of the data based on the error location polynomial.

2. The error correction circuit of claim 1, wherein the number of operation stages used for generating the error location polynomial is greater when the condition information indicates that a probability of an error occurring is high than when the condition information indicates that a probability of an error occurring is low.

3. The error correction circuit of claim 1, wherein the error location polynomial generation block includes:

a plurality of operation stages for sequentially performing an operation using a Berlekamp-Massey (BM) algorithm; and

a selector suitable for selecting one among outputs of the operation stages based on the condition information and transferring the selected output to the chien search block.

4. The error correction circuit of claim 1, wherein the condition information includes at least one among a temperature of a memory storing the data, a refresh cycle of the memory storing the data, an error log record of the memory storing the data, speed information of the memory storing the data, and voltage level information of the memory storing the data.

5. The error correction circuit of claim 4, wherein the condition information generation circuit generates the condition information by reading temperature of a thermometer inside the memory.

6. The error correction circuit of claim 4, wherein the condition information generation circuit generates the condition information by monitoring a refresh command transferred to the memory.

7. The error correction circuit of claim 4, wherein the condition information generation circuit stores a history of errors detected by the error correction circuit and generates the condition information based on the stored history of the errors.

8. The error correction circuit of claim 4, wherein the condition information generation circuit includes a frequency detector for detecting a frequency of a clock that is transferred to the memory, and generates the condition information based on a detection result of the frequency detector.

9. The error correction circuit of claim 4, wherein the condition information generation circuit includes a voltage detector for detecting a level of a power source voltage and generates the condition information based on a detection result of the voltage detector.

10. The error correction circuit of claim 3, wherein the operation stages are coupled in series to repeatedly perform the operation using the BM algorithm.

11. A memory system, comprising:

one or more memories suitable for storing a data and an error correction code;

an error correction code (ECC) generation circuit suitable for generating the error correction code to be programmed in the one or more memories based on the data to be programmed in the one or more memories;

a condition information generation circuit suitable for generating condition information that indicates a probability an error occurring in the one or more memories; and

an error correction circuit suitable for correcting one or more errors of a data that is read from the one or more memories based on the error correction code that is read from the one or more memories, where an error correction intensity is controlled based on the condition information.

12. The memory system of claim 11, wherein the error correction circuit includes:

a syndrome calculation block suitable for generating a syndrome based on the data that is read from the one or more memories and the error correction code that is read from the one or more memories;

an error location polynomial generation block suitable for generating an error location polynomial for detecting one or more locations of one or more errors based on the syndrome, where the number of operation stages used for generating the error location polynomial is controlled based on condition information; and

a chien search block suitable for correcting one or more errors of the data that is read from the one or more memories based on the error location polynomial.

13. The memory system of claim 12, wherein the number of the operation stages used for generating the error location polynomial is greater when the condition information indicates that a probability of an error occurring is high than when the condition information indicates that a probability of an error occurring is low.

14. The memory system of claim 12, wherein the error location polynomial generation block includes:

a plurality of the operation stages for sequentially performing an operation using a Berlekamp-Massey (BM) algorithm; and

a selector suitable for selecting one among outputs of the operation stages based on the condition information and transferring the selected output to the chien search block.

15. The memory system of claim 11, wherein the condition information includes at least one among a temperature of the one or more memories, a refresh cycle of the one or more memories, an error log record of the one or more memories, speed information of the one or more memories, and voltage level information of the one or more memories.

16. The memory system of claim 11, wherein the one or more memories, the ECC generation circuit, the condition information generation circuit, and the error correction circuit are included in a memory module.

17. The memory system of claim 16, wherein the ECC generation circuit, the condition information generation circuit, and the error correction circuit are included in a module controller of the memory module.

18. The memory system of claim 17, wherein the memory system further includes:

a memory controller suitable for controlling the memory module.